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xen-platform: convert to memory API

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Since this device bypasses PCI and registers I/O ports directly with
the system bus, it needs further attention.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2011-08-08 16:09:25 +03:00 committed by Anthony Liguori
parent a03f66e4ac
commit de00982e9e
1 changed files with 50 additions and 33 deletions
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83
hw/xen_platform.c
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@ -32,8 +32,8 @@
#include "xen_common.h" #include "xen_common.h"
#include "net.h" #include "net.h"
#include "xen_backend.h" #include "xen_backend.h"
#include "rwhandler.h"
#include "trace.h" #include "trace.h"
#include "exec-memory.h"
#include <xenguest.h> #include <xenguest.h>
@ -51,6 +51,9 @@
typedef struct PCIXenPlatformState { typedef struct PCIXenPlatformState {
PCIDevice pci_dev; PCIDevice pci_dev;
MemoryRegion fixed_io;
MemoryRegion bar;
MemoryRegion mmio_bar;
uint8_t flags; /* used only for version_id == 2 */ uint8_t flags; /* used only for version_id == 2 */
int drivers_blacklisted; int drivers_blacklisted;
uint16_t driver_product_version; uint16_t driver_product_version;
@ -221,21 +224,32 @@ static void platform_fixed_ioport_reset(void *opaque)
platform_fixed_ioport_writeb(s, XEN_PLATFORM_IOPORT, 0); platform_fixed_ioport_writeb(s, XEN_PLATFORM_IOPORT, 0);
} }
const MemoryRegionPortio xen_platform_ioport[] = {
{ 0, 16, 4, .write = platform_fixed_ioport_writel, },
{ 0, 16, 2, .write = platform_fixed_ioport_writew, },
{ 0, 16, 1, .write = platform_fixed_ioport_writeb, },
{ 0, 16, 2, .read = platform_fixed_ioport_readw, },
{ 0, 16, 1, .read = platform_fixed_ioport_readb, },
PORTIO_END_OF_LIST()
};
static const MemoryRegionOps platform_fixed_io_ops = {
.old_portio = xen_platform_ioport,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void platform_fixed_ioport_init(PCIXenPlatformState* s) static void platform_fixed_ioport_init(PCIXenPlatformState* s)
{ {
register_ioport_write(XEN_PLATFORM_IOPORT, 16, 4, platform_fixed_ioport_writel, s); memory_region_init_io(&s->fixed_io, &platform_fixed_io_ops, s,
register_ioport_write(XEN_PLATFORM_IOPORT, 16, 2, platform_fixed_ioport_writew, s); "xen-fixed", 16);
register_ioport_write(XEN_PLATFORM_IOPORT, 16, 1, platform_fixed_ioport_writeb, s); memory_region_add_subregion(get_system_io(), XEN_PLATFORM_IOPORT,
register_ioport_read(XEN_PLATFORM_IOPORT, 16, 2, platform_fixed_ioport_readw, s); &s->fixed_io);
register_ioport_read(XEN_PLATFORM_IOPORT, 16, 1, platform_fixed_ioport_readb, s);
} }
/* Xen Platform PCI Device */ /* Xen Platform PCI Device */
static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr) static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr)
{ {
addr &= 0xff;
if (addr == 0) { if (addr == 0) {
return platform_fixed_ioport_readb(opaque, XEN_PLATFORM_IOPORT); return platform_fixed_ioport_readb(opaque, XEN_PLATFORM_IOPORT);
} else { } else {
@ -247,9 +261,6 @@ static void xen_platform_ioport_writeb(void *opaque, uint32_t addr, uint32_t val
{ {
PCIXenPlatformState *s = opaque; PCIXenPlatformState *s = opaque;
addr &= 0xff;
val &= 0xff;
switch (addr) { switch (addr) {
case 0: /* Platform flags */ case 0: /* Platform flags */
platform_fixed_ioport_writeb(opaque, XEN_PLATFORM_IOPORT, val); platform_fixed_ioport_writeb(opaque, XEN_PLATFORM_IOPORT, val);
@ -262,15 +273,23 @@ static void xen_platform_ioport_writeb(void *opaque, uint32_t addr, uint32_t val
} }
} }
static void platform_ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr, pcibus_t size, int type) static MemoryRegionPortio xen_pci_portio[] = {
{ { 0, 0x100, 1, .read = xen_platform_ioport_readb, },
PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, pci_dev); { 0, 0x100, 1, .write = xen_platform_ioport_writeb, },
PORTIO_END_OF_LIST()
};
register_ioport_write(addr, size, 1, xen_platform_ioport_writeb, d); static const MemoryRegionOps xen_pci_io_ops = {
register_ioport_read(addr, size, 1, xen_platform_ioport_readb, d); .old_portio = xen_pci_portio,
};
static void platform_ioport_bar_setup(PCIXenPlatformState *d)
{
memory_region_init_io(&d->bar, &xen_pci_io_ops, d, "xen-pci", 0x100);
} }
static uint32_t platform_mmio_read(ReadWriteHandler *handler, pcibus_t addr, int len) static uint64_t platform_mmio_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
DPRINTF("Warning: attempted read from physical address " DPRINTF("Warning: attempted read from physical address "
"0x" TARGET_FMT_plx " in xen platform mmio space\n", addr); "0x" TARGET_FMT_plx " in xen platform mmio space\n", addr);
@ -278,28 +297,24 @@ static uint32_t platform_mmio_read(ReadWriteHandler *handler, pcibus_t addr, int
return 0; return 0;
} }
static void platform_mmio_write(ReadWriteHandler *handler, pcibus_t addr, static void platform_mmio_write(void *opaque, target_phys_addr_t addr,
uint32_t val, int len) uint64_t val, unsigned size)
{ {
DPRINTF("Warning: attempted write of 0x%x to physical " DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
"address 0x" TARGET_FMT_plx " in xen platform mmio space\n", "address 0x" TARGET_FMT_plx " in xen platform mmio space\n",
val, addr); val, addr);
} }
static ReadWriteHandler platform_mmio_handler = { static const MemoryRegionOps platform_mmio_handler = {
.read = &platform_mmio_read, .read = &platform_mmio_read,
.write = &platform_mmio_write, .write = &platform_mmio_write,
.endianness = DEVICE_NATIVE_ENDIAN,
}; };
static void platform_mmio_map(PCIDevice *d, int region_num, static void platform_mmio_setup(PCIXenPlatformState *d)
pcibus_t addr, pcibus_t size, int type)
{ {
int mmio_io_addr; memory_region_init_io(&d->mmio_bar, &platform_mmio_handler, d,
"xen-mmio", 0x1000000);
mmio_io_addr = cpu_register_io_memory_simple(&platform_mmio_handler,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(addr, size, mmio_io_addr);
} }
static int xen_platform_post_load(void *opaque, int version_id) static int xen_platform_post_load(void *opaque, int version_id)
@ -337,12 +352,14 @@ static int xen_platform_initfn(PCIDevice *dev)
pci_conf[PCI_INTERRUPT_PIN] = 1; pci_conf[PCI_INTERRUPT_PIN] = 1;
pci_register_bar(&d->pci_dev, 0, 0x100, platform_ioport_bar_setup(d);
PCI_BASE_ADDRESS_SPACE_IO, platform_ioport_map); pci_register_bar_region(&d->pci_dev, 0,
PCI_BASE_ADDRESS_SPACE_IO, &d->bar);
/* reserve 16MB mmio address for share memory*/ /* reserve 16MB mmio address for share memory*/
pci_register_bar(&d->pci_dev, 1, 0x1000000, platform_mmio_setup(d);
PCI_BASE_ADDRESS_MEM_PREFETCH, platform_mmio_map); pci_register_bar_region(&d->pci_dev, 1,
PCI_BASE_ADDRESS_MEM_PREFETCH, &d->mmio_bar);
platform_fixed_ioport_init(d); platform_fixed_ioport_init(d);