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MAX78000: UART Implementation

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This commit implements UART support for the MAX78000

Signed-off-by: Jackson Donaldson <jcksn@duck.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250704223239.248781-5-jcksn@duck.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jackson Donaldson 2025-07-04 18:32:32 -04:00 committed by Peter Maydell
parent 65714d3e6c
commit d447e4b702
5 changed files with 368 additions and 0 deletions
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1
hw/arm/Kconfig
View File

@ -367,6 +367,7 @@ config MAX78000_SOC
bool
select ARM_V7M
select MAX78000_ICC
select MAX78000_UART
config RASPI
bool

3
hw/char/Kconfig
View File

@ -48,6 +48,9 @@ config VIRTIO_SERIAL
default y
depends on VIRTIO
config MAX78000_UART
bool
config STM32F2XX_USART
bool

285
hw/char/max78000_uart.c Normal file
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@ -0,0 +1,285 @@
/*
* MAX78000 UART
*
* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "hw/char/max78000_uart.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "migration/vmstate.h"
#include "trace.h"
static int max78000_uart_can_receive(void *opaque)
{
Max78000UartState *s = opaque;
if (!(s->ctrl & UART_BCLKEN)) {
return 0;
}
return fifo8_num_free(&s->rx_fifo);
}
static void max78000_update_irq(Max78000UartState *s)
{
int interrupt_level;
interrupt_level = s->int_fl & s->int_en;
qemu_set_irq(s->irq, interrupt_level);
}
static void max78000_uart_receive(void *opaque, const uint8_t *buf, int size)
{
Max78000UartState *s = opaque;
assert(size <= fifo8_num_free(&s->rx_fifo));
fifo8_push_all(&s->rx_fifo, buf, size);
uint32_t rx_threshold = s->ctrl & 0xf;
if (fifo8_num_used(&s->rx_fifo) >= rx_threshold) {
s->int_fl |= UART_RX_THD;
}
max78000_update_irq(s);
}
static void max78000_uart_reset_hold(Object *obj, ResetType type)
{
Max78000UartState *s = MAX78000_UART(obj);
s->ctrl = 0;
s->status = UART_TX_EM | UART_RX_EM;
s->int_en = 0;
s->int_fl = 0;
s->osr = 0;
s->txpeek = 0;
s->pnr = UART_RTS;
s->fifo = 0;
s->dma = 0;
s->wken = 0;
s->wkfl = 0;
fifo8_reset(&s->rx_fifo);
}
static uint64_t max78000_uart_read(void *opaque, hwaddr addr,
unsigned int size)
{
Max78000UartState *s = opaque;
uint64_t retvalue = 0;
switch (addr) {
case UART_CTRL:
retvalue = s->ctrl;
break;
case UART_STATUS:
retvalue = (fifo8_num_used(&s->rx_fifo) << UART_RX_LVL) |
UART_TX_EM |
(fifo8_is_empty(&s->rx_fifo) ? UART_RX_EM : 0);
break;
case UART_INT_EN:
retvalue = s->int_en;
break;
case UART_INT_FL:
retvalue = s->int_fl;
break;
case UART_CLKDIV:
retvalue = s->clkdiv;
break;
case UART_OSR:
retvalue = s->osr;
break;
case UART_TXPEEK:
if (!fifo8_is_empty(&s->rx_fifo)) {
retvalue = fifo8_peek(&s->rx_fifo);
}
break;
case UART_PNR:
retvalue = s->pnr;
break;
case UART_FIFO:
if (!fifo8_is_empty(&s->rx_fifo)) {
retvalue = fifo8_pop(&s->rx_fifo);
max78000_update_irq(s);
}
break;
case UART_DMA:
/* DMA not implemented */
retvalue = s->dma;
break;
case UART_WKEN:
retvalue = s->wken;
break;
case UART_WKFL:
retvalue = s->wkfl;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
break;
}
return retvalue;
}
static void max78000_uart_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
Max78000UartState *s = opaque;
uint32_t value = val64;
uint8_t data;
switch (addr) {
case UART_CTRL:
if (value & UART_FLUSH_RX) {
fifo8_reset(&s->rx_fifo);
}
if (value & UART_BCLKEN) {
value = value | UART_BCLKRDY;
}
s->ctrl = value & ~(UART_FLUSH_RX | UART_FLUSH_TX);
/*
* Software can manage UART flow control manually by setting hfc_en
* in UART_CTRL. This would require emulating uart at a lower level,
* and is currently unimplemented.
*/
return;
case UART_STATUS:
/* UART_STATUS is read only */
return;
case UART_INT_EN:
s->int_en = value;
return;
case UART_INT_FL:
s->int_fl = s->int_fl & ~(value);
max78000_update_irq(s);
return;
case UART_CLKDIV:
s->clkdiv = value;
return;
case UART_OSR:
s->osr = value;
return;
case UART_PNR:
s->pnr = value;
return;
case UART_FIFO:
data = value & 0xff;
/*
* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks
*/
qemu_chr_fe_write_all(&s->chr, &data, 1);
/* TX is always empty */
s->int_fl |= UART_TX_HE;
max78000_update_irq(s);
return;
case UART_DMA:
/* DMA not implemented */
s->dma = value;
return;
case UART_WKEN:
s->wken = value;
return;
case UART_WKFL:
s->wkfl = value;
return;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"
HWADDR_PRIx "\n", __func__, addr);
}
}
static const MemoryRegionOps max78000_uart_ops = {
.read = max78000_uart_read,
.write = max78000_uart_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid.min_access_size = 4,
.valid.max_access_size = 4,
};
static const Property max78000_uart_properties[] = {
DEFINE_PROP_CHR("chardev", Max78000UartState, chr),
};
static const VMStateDescription max78000_uart_vmstate = {
.name = TYPE_MAX78000_UART,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(ctrl, Max78000UartState),
VMSTATE_UINT32(status, Max78000UartState),
VMSTATE_UINT32(int_en, Max78000UartState),
VMSTATE_UINT32(int_fl, Max78000UartState),
VMSTATE_UINT32(clkdiv, Max78000UartState),
VMSTATE_UINT32(osr, Max78000UartState),
VMSTATE_UINT32(txpeek, Max78000UartState),
VMSTATE_UINT32(pnr, Max78000UartState),
VMSTATE_UINT32(fifo, Max78000UartState),
VMSTATE_UINT32(dma, Max78000UartState),
VMSTATE_UINT32(wken, Max78000UartState),
VMSTATE_UINT32(wkfl, Max78000UartState),
VMSTATE_FIFO8(rx_fifo, Max78000UartState),
VMSTATE_END_OF_LIST()
}
};
static void max78000_uart_init(Object *obj)
{
Max78000UartState *s = MAX78000_UART(obj);
fifo8_create(&s->rx_fifo, 8);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
memory_region_init_io(&s->mmio, obj, &max78000_uart_ops, s,
TYPE_MAX78000_UART, 0x400);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
}
static void max78000_uart_realize(DeviceState *dev, Error **errp)
{
Max78000UartState *s = MAX78000_UART(dev);
qemu_chr_fe_set_handlers(&s->chr, max78000_uart_can_receive,
max78000_uart_receive, NULL, NULL,
s, NULL, true);
}
static void max78000_uart_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
ResettableClass *rc = RESETTABLE_CLASS(klass);
rc->phases.hold = max78000_uart_reset_hold;
device_class_set_props(dc, max78000_uart_properties);
dc->realize = max78000_uart_realize;
dc->vmsd = &max78000_uart_vmstate;
}
static const TypeInfo max78000_uart_info = {
.name = TYPE_MAX78000_UART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Max78000UartState),
.instance_init = max78000_uart_init,
.class_init = max78000_uart_class_init,
};
static void max78000_uart_register_types(void)
{
type_register_static(&max78000_uart_info);
}
type_init(max78000_uart_register_types)

1
hw/char/meson.build
View File

@ -26,6 +26,7 @@ system_ss.add(when: 'CONFIG_AVR_USART', if_true: files('avr_usart.c'))
system_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_uart.c'))
system_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic-uart.c'))
system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c'))
system_ss.add(when: 'CONFIG_MAX78000_UART', if_true: files('max78000_uart.c'))
system_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c'))
system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
system_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))

78
include/hw/char/max78000_uart.h Normal file
View File

@ -0,0 +1,78 @@
/*
* MAX78000 UART
*
* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_MAX78000_UART_H
#define HW_MAX78000_UART_H
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "qemu/fifo8.h"
#include "qom/object.h"
#define UART_CTRL 0x0
#define UART_STATUS 0x4
#define UART_INT_EN 0x8
#define UART_INT_FL 0xc
#define UART_CLKDIV 0x10
#define UART_OSR 0x14
#define UART_TXPEEK 0x18
#define UART_PNR 0x1c
#define UART_FIFO 0x20
#define UART_DMA 0x30
#define UART_WKEN 0x34
#define UART_WKFL 0x38
/* CTRL */
#define UART_CTF_DIS (1 << 7)
#define UART_FLUSH_TX (1 << 8)
#define UART_FLUSH_RX (1 << 9)
#define UART_BCLKEN (1 << 15)
#define UART_BCLKRDY (1 << 19)
/* STATUS */
#define UART_RX_LVL 8
#define UART_TX_EM (1 << 6)
#define UART_RX_FULL (1 << 5)
#define UART_RX_EM (1 << 4)
/* PNR (Pin Control Register) */
#define UART_CTS 1
#define UART_RTS (1 << 1)
/* INT_EN / INT_FL */
#define UART_RX_THD (1 << 4)
#define UART_TX_HE (1 << 6)
#define UART_RXBUFLEN 0x100
#define TYPE_MAX78000_UART "max78000-uart"
OBJECT_DECLARE_SIMPLE_TYPE(Max78000UartState, MAX78000_UART)
struct Max78000UartState {
SysBusDevice parent_obj;
MemoryRegion mmio;
uint32_t ctrl;
uint32_t status;
uint32_t int_en;
uint32_t int_fl;
uint32_t clkdiv;
uint32_t osr;
uint32_t txpeek;
uint32_t pnr;
uint32_t fifo;
uint32_t dma;
uint32_t wken;
uint32_t wkfl;
Fifo8 rx_fifo;
CharBackend chr;
qemu_irq irq;
};
#endif /* HW_STM32F2XX_USART_H */