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target/microblaze: Fix width of BTR

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The branch target register is only 32-bits wide.  Do not use a
64-bit type to represent it.  Since cpu_btr is only used during
MSR and MTR instructions, we can just as easily use an explicit
load and store, so eliminate the variable.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-08-19 22:44:49 -07:00
parent 86017ccfbd
commit ccf628b793
2 changed files with 6 additions and 8 deletions
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2
target/microblaze/cpu.h
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@ -241,7 +241,7 @@ struct CPUMBState {
uint64_t ear;
uint32_t esr;
uint32_t fsr;
uint64_t btr;
uint32_t btr;
uint64_t edr;
float_status fp_status;
/* Stack protectors. Yes, it's a hw feature. */

12
target/microblaze/translate.c
View File

@ -59,7 +59,6 @@ static TCGv_i32 cpu_pc;
static TCGv_i32 cpu_msr;
static TCGv_i64 cpu_ear;
static TCGv_i32 cpu_esr;
static TCGv_i64 cpu_btr;
static TCGv_i64 cpu_edr;
static TCGv_i32 env_imm;
static TCGv_i32 env_btaken;
@ -545,7 +544,8 @@ static void dec_msr(DisasContext *dc)
cpu_env, offsetof(CPUMBState, fsr));
break;
case SR_BTR:
tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]);
tcg_gen_st_i32(cpu_R[dc->ra],
cpu_env, offsetof(CPUMBState, btr));
break;
case SR_EDR:
tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]);
@ -587,7 +587,8 @@ static void dec_msr(DisasContext *dc)
cpu_env, offsetof(CPUMBState, fsr));
break;
case SR_BTR:
tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr);
tcg_gen_ld_i32(cpu_R[dc->rd],
cpu_env, offsetof(CPUMBState, btr));
break;
case SR_EDR:
tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr);
@ -1799,8 +1800,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "IN: PC=%x %s\n",
env->pc, lookup_symbol(env->pc));
qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " "
"debug=%x imm=%x iflags=%x fsr=%x "
"rbtr=%" PRIx64 "\n",
"debug=%x imm=%x iflags=%x fsr=%x rbtr=%x\n",
env->msr, env->esr, env->ear,
env->debug, env->imm, env->iflags, env->fsr,
env->btr);
@ -1868,8 +1868,6 @@ void mb_tcg_init(void)
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
cpu_esr =
tcg_global_mem_new_i32(cpu_env, offsetof(CPUMBState, esr), "resr");
cpu_btr =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr");
cpu_edr =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr");
}