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hw/misc: Move NPCM7XX CLK to NPCM CLK

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A lot of NPCM7XX and NPCM8XX CLK modules share the same code,
this commit moves the NPCM7XX CLK to NPCM CLK for these
properties.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20250219184609.1839281-12-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Hao Wu 2025-02-19 10:46:02 -08:00 committed by Peter Maydell
parent c8283b0f4a
commit ca6d6a94f4
4 changed files with 77 additions and 61 deletions
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106
hw/misc/npcm_clk.c
View File

@ -198,7 +198,7 @@ static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
} }
} }
static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk) static void npcm7xx_clk_update_all_plls(NPCMCLKState *clk)
{ {
int i; int i;
@ -207,7 +207,7 @@ static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
} }
} }
static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk) static void npcm7xx_clk_update_all_sels(NPCMCLKState *clk)
{ {
int i; int i;
@ -216,7 +216,7 @@ static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
} }
} }
static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk) static void npcm7xx_clk_update_all_dividers(NPCMCLKState *clk)
{ {
int i; int i;
@ -225,7 +225,7 @@ static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
} }
} }
static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk) static void npcm7xx_clk_update_all_clocks(NPCMCLKState *clk)
{ {
clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ); clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
npcm7xx_clk_update_all_plls(clk); npcm7xx_clk_update_all_plls(clk);
@ -635,7 +635,7 @@ static void npcm7xx_clk_divider_init(Object *obj)
} }
static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll, static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
NPCM7xxCLKState *clk, const PLLInitInfo *init_info) NPCMCLKState *clk, const PLLInitInfo *init_info)
{ {
pll->name = init_info->name; pll->name = init_info->name;
pll->clk = clk; pll->clk = clk;
@ -647,7 +647,7 @@ static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
} }
static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel, static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
NPCM7xxCLKState *clk, const SELInitInfo *init_info) NPCMCLKState *clk, const SELInitInfo *init_info)
{ {
int input_size = init_info->input_size; int input_size = init_info->input_size;
@ -664,7 +664,7 @@ static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
} }
static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div, static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
NPCM7xxCLKState *clk, const DividerInitInfo *init_info) NPCMCLKState *clk, const DividerInitInfo *init_info)
{ {
div->name = init_info->name; div->name = init_info->name;
div->clk = clk; div->clk = clk;
@ -683,7 +683,7 @@ static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
} }
} }
static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type, static Clock *npcm7xx_get_clock(NPCMCLKState *clk, ClockSrcType type,
int index) int index)
{ {
switch (type) { switch (type) {
@ -700,7 +700,7 @@ static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
} }
} }
static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk) static void npcm7xx_connect_clocks(NPCMCLKState *clk)
{ {
int i, j; int i, j;
Clock *src; Clock *src;
@ -724,10 +724,10 @@ static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
} }
} }
static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size) static uint64_t npcm_clk_read(void *opaque, hwaddr offset, unsigned size)
{ {
uint32_t reg = offset / sizeof(uint32_t); uint32_t reg = offset / sizeof(uint32_t);
NPCM7xxCLKState *s = opaque; NPCMCLKState *s = opaque;
int64_t now_ns; int64_t now_ns;
uint32_t value = 0; uint32_t value = 0;
@ -766,19 +766,19 @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
break; break;
}; };
trace_npcm7xx_clk_read(offset, value); trace_npcm_clk_read(offset, value);
return value; return value;
} }
static void npcm7xx_clk_write(void *opaque, hwaddr offset, static void npcm_clk_write(void *opaque, hwaddr offset,
uint64_t v, unsigned size) uint64_t v, unsigned size)
{ {
uint32_t reg = offset / sizeof(uint32_t); uint32_t reg = offset / sizeof(uint32_t);
NPCM7xxCLKState *s = opaque; NPCMCLKState *s = opaque;
uint32_t value = v; uint32_t value = v;
trace_npcm7xx_clk_write(offset, value); trace_npcm_clk_write(offset, value);
if (reg >= NPCM7XX_CLK_NR_REGS) { if (reg >= NPCM7XX_CLK_NR_REGS) {
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
@ -842,7 +842,7 @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n, static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n,
int level) int level)
{ {
NPCM7xxCLKState *clk = NPCM7XX_CLK(opaque); NPCMCLKState *clk = NPCM_CLK(opaque);
uint32_t rcr; uint32_t rcr;
g_assert(n >= 0 && n <= NPCM7XX_NR_WATCHDOGS); g_assert(n >= 0 && n <= NPCM7XX_NR_WATCHDOGS);
@ -856,9 +856,9 @@ static void npcm7xx_clk_perform_watchdog_reset(void *opaque, int n,
} }
} }
static const struct MemoryRegionOps npcm7xx_clk_ops = { static const struct MemoryRegionOps npcm_clk_ops = {
.read = npcm7xx_clk_read, .read = npcm_clk_read,
.write = npcm7xx_clk_write, .write = npcm_clk_write,
.endianness = DEVICE_LITTLE_ENDIAN, .endianness = DEVICE_LITTLE_ENDIAN,
.valid = { .valid = {
.min_access_size = 4, .min_access_size = 4,
@ -867,9 +867,9 @@ static const struct MemoryRegionOps npcm7xx_clk_ops = {
}, },
}; };
static void npcm7xx_clk_enter_reset(Object *obj, ResetType type) static void npcm_clk_enter_reset(Object *obj, ResetType type)
{ {
NPCM7xxCLKState *s = NPCM7XX_CLK(obj); NPCMCLKState *s = NPCM_CLK(obj);
QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values)); QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
@ -882,7 +882,7 @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
*/ */
} }
static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s) static void npcm7xx_clk_init_clock_hierarchy(NPCMCLKState *s)
{ {
int i; int i;
@ -918,19 +918,19 @@ static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ); clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
} }
static void npcm7xx_clk_init(Object *obj) static void npcm_clk_init(Object *obj)
{ {
NPCM7xxCLKState *s = NPCM7XX_CLK(obj); NPCMCLKState *s = NPCM_CLK(obj);
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s, memory_region_init_io(&s->iomem, obj, &npcm_clk_ops, s,
TYPE_NPCM7XX_CLK, 4 * KiB); TYPE_NPCM_CLK, 4 * KiB);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
} }
static int npcm7xx_clk_post_load(void *opaque, int version_id) static int npcm_clk_post_load(void *opaque, int version_id)
{ {
if (version_id >= 1) { if (version_id >= 1) {
NPCM7xxCLKState *clk = opaque; NPCMCLKState *clk = opaque;
npcm7xx_clk_update_all_clocks(clk); npcm7xx_clk_update_all_clocks(clk);
} }
@ -938,10 +938,10 @@ static int npcm7xx_clk_post_load(void *opaque, int version_id)
return 0; return 0;
} }
static void npcm7xx_clk_realize(DeviceState *dev, Error **errp) static void npcm_clk_realize(DeviceState *dev, Error **errp)
{ {
int i; int i;
NPCM7xxCLKState *s = NPCM7XX_CLK(dev); NPCMCLKState *s = NPCM_CLK(dev);
qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset, qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS); NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
@ -996,15 +996,15 @@ static const VMStateDescription vmstate_npcm7xx_clk_divider = {
}, },
}; };
static const VMStateDescription vmstate_npcm7xx_clk = { static const VMStateDescription vmstate_npcm_clk = {
.name = "npcm7xx-clk", .name = "npcm-clk",
.version_id = 1, .version_id = 2,
.minimum_version_id = 1, .minimum_version_id = 2,
.post_load = npcm7xx_clk_post_load, .post_load = npcm_clk_post_load,
.fields = (const VMStateField[]) { .fields = (const VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS), VMSTATE_UINT32_ARRAY(regs, NPCMCLKState, NPCM_CLK_MAX_NR_REGS),
VMSTATE_INT64(ref_ns, NPCM7xxCLKState), VMSTATE_INT64(ref_ns, NPCMCLKState),
VMSTATE_CLOCK(clkref, NPCM7xxCLKState), VMSTATE_CLOCK(clkref, NPCMCLKState),
VMSTATE_END_OF_LIST(), VMSTATE_END_OF_LIST(),
}, },
}; };
@ -1033,17 +1033,23 @@ static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_npcm7xx_clk_divider; dc->vmsd = &vmstate_npcm7xx_clk_divider;
} }
static void npcm7xx_clk_class_init(ObjectClass *klass, void *data) static void npcm_clk_class_init(ObjectClass *klass, void *data)
{ {
ResettableClass *rc = RESETTABLE_CLASS(klass); ResettableClass *rc = RESETTABLE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM7XX_CLK_NR_REGS); dc->vmsd = &vmstate_npcm_clk;
dc->realize = npcm_clk_realize;
rc->phases.enter = npcm_clk_enter_reset;
}
static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END > NPCM_CLK_MAX_NR_REGS);
QEMU_BUILD_BUG_ON(NPCM7XX_CLK_REGS_END != NPCM7XX_CLK_NR_REGS);
dc->desc = "NPCM7xx Clock Control Registers"; dc->desc = "NPCM7xx Clock Control Registers";
dc->vmsd = &vmstate_npcm7xx_clk;
dc->realize = npcm7xx_clk_realize;
rc->phases.enter = npcm7xx_clk_enter_reset;
} }
static const TypeInfo npcm7xx_clk_pll_info = { static const TypeInfo npcm7xx_clk_pll_info = {
@ -1070,11 +1076,18 @@ static const TypeInfo npcm7xx_clk_divider_info = {
.class_init = npcm7xx_clk_divider_class_init, .class_init = npcm7xx_clk_divider_class_init,
}; };
static const TypeInfo npcm_clk_info = {
.name = TYPE_NPCM_CLK,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(NPCMCLKState),
.instance_init = npcm_clk_init,
.class_init = npcm_clk_class_init,
.abstract = true,
};
static const TypeInfo npcm7xx_clk_info = { static const TypeInfo npcm7xx_clk_info = {
.name = TYPE_NPCM7XX_CLK, .name = TYPE_NPCM7XX_CLK,
.parent = TYPE_SYS_BUS_DEVICE, .parent = TYPE_NPCM_CLK,
.instance_size = sizeof(NPCM7xxCLKState),
.instance_init = npcm7xx_clk_init,
.class_init = npcm7xx_clk_class_init, .class_init = npcm7xx_clk_class_init,
}; };
@ -1083,6 +1096,7 @@ static void npcm7xx_clk_register_type(void)
type_register_static(&npcm7xx_clk_pll_info); type_register_static(&npcm7xx_clk_pll_info);
type_register_static(&npcm7xx_clk_sel_info); type_register_static(&npcm7xx_clk_sel_info);
type_register_static(&npcm7xx_clk_divider_info); type_register_static(&npcm7xx_clk_divider_info);
type_register_static(&npcm_clk_info);
type_register_static(&npcm7xx_clk_info); type_register_static(&npcm7xx_clk_info);
} }
type_init(npcm7xx_clk_register_type); type_init(npcm7xx_clk_register_type);

6
hw/misc/trace-events
View File

@ -130,9 +130,9 @@ mos6522_set_sr_int(void) "set sr_int"
mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64 mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64
mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x" mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x"
# npcm7xx_clk.c # npcm_clk.c
npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 npcm_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 npcm_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
# npcm_gcr.c # npcm_gcr.c
npcm_gcr_read(uint64_t offset, uint64_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx64 npcm_gcr_read(uint64_t offset, uint64_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx64

2
include/hw/arm/npcm7xx.h
View File

@ -90,7 +90,7 @@ struct NPCM7xxState {
MemoryRegion *dram; MemoryRegion *dram;
NPCMGCRState gcr; NPCMGCRState gcr;
NPCM7xxCLKState clk; NPCMCLKState clk;
NPCM7xxTimerCtrlState tim[3]; NPCM7xxTimerCtrlState tim[3];
NPCM7xxADCState adc; NPCM7xxADCState adc;
NPCM7xxPWMState pwm[NPCM7XX_NR_PWM_MODULES]; NPCM7xxPWMState pwm[NPCM7XX_NR_PWM_MODULES];

24
include/hw/misc/npcm_clk.h
View File

@ -20,11 +20,12 @@
#include "hw/clock.h" #include "hw/clock.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
/*
* Number of registers in our device state structure. Don't change this without
* incrementing the version_id in the vmstate.
*/
#define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t)) #define NPCM7XX_CLK_NR_REGS (0x70 / sizeof(uint32_t))
/*
* Number of maximum registers in NPCM device state structure. Don't change
* this without incrementing the version_id in the vmstate.
*/
#define NPCM_CLK_MAX_NR_REGS NPCM7XX_CLK_NR_REGS
#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
@ -80,7 +81,7 @@ typedef enum NPCM7xxClockDivider {
NPCM7XX_CLOCK_NR_DIVIDERS, NPCM7XX_CLOCK_NR_DIVIDERS,
} NPCM7xxClockConverter; } NPCM7xxClockConverter;
typedef struct NPCM7xxCLKState NPCM7xxCLKState; typedef struct NPCMCLKState NPCMCLKState;
/** /**
* struct NPCM7xxClockPLLState - A PLL module in CLK module. * struct NPCM7xxClockPLLState - A PLL module in CLK module.
@ -94,7 +95,7 @@ typedef struct NPCM7xxClockPLLState {
DeviceState parent; DeviceState parent;
const char *name; const char *name;
NPCM7xxCLKState *clk; NPCMCLKState *clk;
Clock *clock_in; Clock *clock_in;
Clock *clock_out; Clock *clock_out;
@ -115,7 +116,7 @@ typedef struct NPCM7xxClockSELState {
DeviceState parent; DeviceState parent;
const char *name; const char *name;
NPCM7xxCLKState *clk; NPCMCLKState *clk;
uint8_t input_size; uint8_t input_size;
Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT]; Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
Clock *clock_out; Clock *clock_out;
@ -140,7 +141,7 @@ typedef struct NPCM7xxClockDividerState {
DeviceState parent; DeviceState parent;
const char *name; const char *name;
NPCM7xxCLKState *clk; NPCMCLKState *clk;
Clock *clock_in; Clock *clock_in;
Clock *clock_out; Clock *clock_out;
@ -155,7 +156,7 @@ typedef struct NPCM7xxClockDividerState {
}; };
} NPCM7xxClockDividerState; } NPCM7xxClockDividerState;
struct NPCM7xxCLKState { struct NPCMCLKState {
SysBusDevice parent; SysBusDevice parent;
MemoryRegion iomem; MemoryRegion iomem;
@ -165,7 +166,7 @@ struct NPCM7xxCLKState {
NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS]; NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS]; NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
uint32_t regs[NPCM7XX_CLK_NR_REGS]; uint32_t regs[NPCM_CLK_MAX_NR_REGS];
/* Time reference for SECCNT and CNTR25M, initialized by power on reset */ /* Time reference for SECCNT and CNTR25M, initialized by power on reset */
int64_t ref_ns; int64_t ref_ns;
@ -174,7 +175,8 @@ struct NPCM7xxCLKState {
Clock *clkref; Clock *clkref;
}; };
#define TYPE_NPCM_CLK "npcm-clk"
OBJECT_DECLARE_SIMPLE_TYPE(NPCMCLKState, NPCM_CLK)
#define TYPE_NPCM7XX_CLK "npcm7xx-clk" #define TYPE_NPCM7XX_CLK "npcm7xx-clk"
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK)
#endif /* NPCM_CLK_H */ #endif /* NPCM_CLK_H */