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aspeed/scu: Create separate write callbacks
This splits the common write callback into separate ast2400 and ast2500 implementations. This makes it clearer when implementing differing behaviour. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200121013302.43839-2-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -232,8 +232,47 @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
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return s->regs[reg];
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return s->regs[reg];
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}
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}
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static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
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static void aspeed_ast2400_scu_write(void *opaque, hwaddr offset,
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unsigned size)
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uint64_t data, unsigned size)
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{
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AspeedSCUState *s = ASPEED_SCU(opaque);
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int reg = TO_REG(offset);
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if (reg >= ASPEED_SCU_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return;
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}
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if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
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!s->regs[PROT_KEY]) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
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}
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trace_aspeed_scu_write(offset, size, data);
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switch (reg) {
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case PROT_KEY:
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s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
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return;
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case SILICON_REV:
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case FREQ_CNTR_EVAL:
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case VGA_SCRATCH1 ... VGA_SCRATCH8:
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case RNG_DATA:
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case FREE_CNTR4:
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case FREE_CNTR4_EXT:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return;
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}
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s->regs[reg] = data;
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}
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static void aspeed_ast2500_scu_write(void *opaque, hwaddr offset,
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uint64_t data, unsigned size)
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{
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{
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AspeedSCUState *s = ASPEED_SCU(opaque);
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AspeedSCUState *s = ASPEED_SCU(opaque);
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int reg = TO_REG(offset);
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int reg = TO_REG(offset);
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@ -257,25 +296,11 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
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case PROT_KEY:
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case PROT_KEY:
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s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
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s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
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return;
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return;
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case CLK_SEL:
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s->regs[reg] = data;
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break;
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case HW_STRAP1:
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case HW_STRAP1:
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if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
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s->regs[HW_STRAP1] |= data;
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s->regs[HW_STRAP1] |= data;
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return;
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return;
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}
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/* Jump to assignment below */
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break;
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case SILICON_REV:
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case SILICON_REV:
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if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
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s->regs[HW_STRAP1] &= ~data;
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s->regs[HW_STRAP1] &= ~data;
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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}
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/* Avoid assignment below, we've handled everything */
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return;
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return;
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case FREQ_CNTR_EVAL:
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case FREQ_CNTR_EVAL:
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case VGA_SCRATCH1 ... VGA_SCRATCH8:
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case VGA_SCRATCH1 ... VGA_SCRATCH8:
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@ -291,9 +316,18 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
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s->regs[reg] = data;
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s->regs[reg] = data;
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}
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}
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static const MemoryRegionOps aspeed_scu_ops = {
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static const MemoryRegionOps aspeed_ast2400_scu_ops = {
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.read = aspeed_scu_read,
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.read = aspeed_scu_read,
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.write = aspeed_scu_write,
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.write = aspeed_ast2400_scu_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.valid.unaligned = false,
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};
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static const MemoryRegionOps aspeed_ast2500_scu_ops = {
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.read = aspeed_scu_read,
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.write = aspeed_ast2500_scu_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.valid.max_access_size = 4,
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@ -469,7 +503,7 @@ static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data)
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asc->calc_hpll = aspeed_2400_scu_calc_hpll;
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asc->calc_hpll = aspeed_2400_scu_calc_hpll;
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asc->apb_divider = 2;
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asc->apb_divider = 2;
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asc->nr_regs = ASPEED_SCU_NR_REGS;
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asc->nr_regs = ASPEED_SCU_NR_REGS;
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asc->ops = &aspeed_scu_ops;
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asc->ops = &aspeed_ast2400_scu_ops;
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}
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}
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static const TypeInfo aspeed_2400_scu_info = {
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static const TypeInfo aspeed_2400_scu_info = {
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@ -489,7 +523,7 @@ static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data)
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asc->calc_hpll = aspeed_2500_scu_calc_hpll;
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asc->calc_hpll = aspeed_2500_scu_calc_hpll;
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asc->apb_divider = 4;
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asc->apb_divider = 4;
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asc->nr_regs = ASPEED_SCU_NR_REGS;
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asc->nr_regs = ASPEED_SCU_NR_REGS;
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asc->ops = &aspeed_scu_ops;
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asc->ops = &aspeed_ast2500_scu_ops;
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}
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}
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static const TypeInfo aspeed_2500_scu_info = {
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static const TypeInfo aspeed_2500_scu_info = {
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