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target/mips: Add placeholder and invocation of decode_nanomips_opc()

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Add empty body and invocation of decode_nanomips_opc() if the bit
ISA_NANOMIPS32 is set in ctx->insn_flags.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
This commit is contained in:
Aleksandar Markovic 2018-08-02 16:16:04 +02:00
parent 0bbc039680
commit c533c0f474
1 changed files with 17 additions and 1 deletions
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18
target/mips/translate.c
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@ -16586,6 +16586,19 @@ enum {
NM_EVP = 0x01, NM_EVP = 0x01,
}; };
/*
*
* nanoMIPS decoding engine
*
*/
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
return 2;
}
/* SmartMIPS extension to MIPS32 */ /* SmartMIPS extension to MIPS32 */
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
@ -21402,7 +21415,10 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
int is_slot; int is_slot;
is_slot = ctx->hflags & MIPS_HFLAG_BMASK; is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
if (!(ctx->hflags & MIPS_HFLAG_M16)) { if (ctx->insn_flags & ISA_NANOMIPS32) {
ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
insn_bytes = decode_nanomips_opc(env, ctx);
} else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
insn_bytes = 4; insn_bytes = 4;
decode_opc(env, ctx); decode_opc(env, ctx);