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linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI

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Transform the prot bit to a qemu internal page bit, and save
it in the page tables.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201021173749.111103-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-10-21 10:37:39 -07:00 committed by Peter Maydell
parent 0b6a03c044
commit be5d6f4884
5 changed files with 30 additions and 3 deletions
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2
include/exec/cpu-all.h
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@ -274,6 +274,8 @@ extern intptr_t qemu_host_page_mask;
/* FIXME: Code that sets/uses this is broken and needs to go away. */ /* FIXME: Code that sets/uses this is broken and needs to go away. */
#define PAGE_RESERVED 0x0020 #define PAGE_RESERVED 0x0020
#endif #endif
/* Target-specific bits that will be used via page_get_flags(). */
#define PAGE_TARGET_1 0x0080
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
void page_dump(FILE *f); void page_dump(FILE *f);

16
linux-user/mmap.c
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@ -83,6 +83,22 @@ static int validate_prot_to_pageflags(int *host_prot, int prot)
*host_prot = (prot & (PROT_READ | PROT_WRITE)) *host_prot = (prot & (PROT_READ | PROT_WRITE))
| (prot & PROT_EXEC ? PROT_READ : 0); | (prot & PROT_EXEC ? PROT_READ : 0);
#ifdef TARGET_AARCH64
/*
* The PROT_BTI bit is only accepted if the cpu supports the feature.
* Since this is the unusual case, don't bother checking unless
* the bit has been requested. If set and valid, record the bit
* within QEMU's page_flags.
*/
if (prot & TARGET_PROT_BTI) {
ARMCPU *cpu = ARM_CPU(thread_cpu);
if (cpu_isar_feature(aa64_bti, cpu)) {
valid |= TARGET_PROT_BTI;
page_flags |= PAGE_BTI;
}
}
#endif
return prot & ~valid ? 0 : page_flags; return prot & ~valid ? 0 : page_flags;
} }

4
linux-user/syscall_defs.h
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@ -1277,6 +1277,10 @@ struct target_winsize {
#define TARGET_PROT_SEM 0x08 #define TARGET_PROT_SEM 0x08
#endif #endif
#ifdef TARGET_AARCH64
#define TARGET_PROT_BTI 0x10
#endif
/* Common */ /* Common */
#define TARGET_MAP_SHARED 0x01 /* Share changes */ #define TARGET_MAP_SHARED 0x01 /* Share changes */
#define TARGET_MAP_PRIVATE 0x02 /* Changes are private */ #define TARGET_MAP_PRIVATE 0x02 /* Changes are private */

5
target/arm/cpu.h
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@ -3445,6 +3445,11 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
#define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
/*
* AArch64 usage of the PAGE_TARGET_* bits for linux-user.
*/
#define PAGE_BTI PAGE_TARGET_1
/* /*
* Naming convention for isar_feature functions: * Naming convention for isar_feature functions:
* Functions which test 32-bit ID registers should have _aa32_ in * Functions which test 32-bit ID registers should have _aa32_ in

6
target/arm/translate-a64.c
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@ -14507,10 +14507,10 @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
*/ */
static bool is_guarded_page(CPUARMState *env, DisasContext *s) static bool is_guarded_page(CPUARMState *env, DisasContext *s)
{ {
#ifdef CONFIG_USER_ONLY
return false; /* FIXME */
#else
uint64_t addr = s->base.pc_first; uint64_t addr = s->base.pc_first;
#ifdef CONFIG_USER_ONLY
return page_get_flags(addr) & PAGE_BTI;
#else
int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx);
unsigned int index = tlb_index(env, mmu_idx, addr); unsigned int index = tlb_index(env, mmu_idx, addr);
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);