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microvm: add pcie support.
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABCgAGBQJfdMT5AAoJEEy22O7T6HE4QHkQAKBLDfVAoogJTQgKcgKKVAfb vxH+c0zIX4bXlh+/+aAShXf/1To1BkZtbIxYJX2hx9oec3zO+DK+p1YrAK8O0Lcz hleEyVpYhhX90y0HDzFlF9q05O90vYP+hzj8VW+IgkOJ7nWG+KdkiRBkxlwvn0PJ Zw4qw9fjZ/MW0Ml2UVQv2lfAaTc8XiasZo1ZEfZ8rK/a0ut+0wLefzWzqm//bJD+ Ek2x9Om3okg2emeuBkeSWLlZ40fMGfEXn4UQkE7ZCLN6Q/LqSdEIn00MSjJa8C4T Z3CVNeHRlgG9C80tbM6rs+2YbWhBj0RPa7woNGZmVJaLIsBrMSC5s9ifvvnamtnE wzBm9Qayv67BcQHZOgEgxrSrNc7/tibwvcpGfiT9ONz/PVbMO7eTlRGFnwNGh2Fv 0caPb8Ge9PLyfc7BXLday/0RM91lu3zTOlnfm6U/KFWPucF+zMFN5KCAGyqComxk g+1VxPPpXtCcIFwGYZ1yesKTW6VHFUEb6v5+gkU1UUJhSoz6141AR72DNFm2NA0j gk9GJ5ZZzMlFQV6YcrGkpFo0q0DKqSMy3dU1HjT7zMbh09hhJqdT1dyIBEfxJpgu LvDI318bvBjwqkdnlRxwQ01GZ3HGGkga0UHjz1LbeYlR59UC2wJWtCoMRYt9Oms4 d+b7Fmbec2tU18uVtSOP =BHn7 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/kraxel/tags/microvm-20200930-pull-request' into staging microvm: add pcie support. # gpg: Signature made Wed 30 Sep 2020 18:48:41 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/microvm-20200930-pull-request: tests/acpi: update expected data files acpi/gpex: no reason to use a method for _CRS tests/acpi: add microvm pcie test tests/acpi: factor out common microvm test setup tests/acpi: add empty tests/data/acpi/microvm/DSDT.pcie file tests/acpi: allow updates for expected data files microvm/pcie: add 64bit mmio window microvm: add pcie support microvm: add irq table arm: use acpi_dsdt_add_gpex acpi: add acpi_dsdt_add_gpex move MemMapEntry Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
b23317eec4
@ -80,11 +80,6 @@ enum {
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SBSA_EHCI,
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SBSA_EHCI,
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};
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};
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typedef struct MemMapEntry {
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hwaddr base;
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hwaddr size;
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} MemMapEntry;
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struct SBSAMachineState {
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struct SBSAMachineState {
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MachineState parent;
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MachineState parent;
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struct arm_boot_info bootinfo;
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struct arm_boot_info bootinfo;
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@ -44,6 +44,7 @@
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#include "hw/acpi/tpm.h"
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#include "hw/acpi/tpm.h"
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#include "hw/pci/pcie_host.h"
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#include "hw/pci/pcie_host.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci.h"
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#include "hw/pci-host/gpex.h"
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#include "hw/arm/virt.h"
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#include "hw/arm/virt.h"
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#include "hw/mem/nvdimm.h"
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#include "hw/mem/nvdimm.h"
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#include "hw/platform-bus.h"
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#include "hw/platform-bus.h"
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@ -155,176 +156,18 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
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uint32_t irq, bool use_highmem, bool highmem_ecam)
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uint32_t irq, bool use_highmem, bool highmem_ecam)
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{
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{
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int ecam_id = VIRT_ECAM_ID(highmem_ecam);
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int ecam_id = VIRT_ECAM_ID(highmem_ecam);
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Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
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struct GPEXConfig cfg = {
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int i, slot_no;
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.mmio32 = memmap[VIRT_PCIE_MMIO],
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hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
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.pio = memmap[VIRT_PCIE_PIO],
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hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
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.ecam = memmap[ecam_id],
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hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
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.irq = irq,
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hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
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};
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hwaddr base_ecam = memmap[ecam_id].base;
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hwaddr size_ecam = memmap[ecam_id].size;
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int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
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Aml *dev = aml_device("%s", "PCI0");
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aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
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aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
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aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
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aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
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aml_append(dev, aml_name_decl("_UID", aml_int(0)));
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aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
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aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
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/* Declare the PCI Routing Table. */
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Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS);
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for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) {
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for (i = 0; i < PCI_NUM_PINS; i++) {
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int gsi = (i + slot_no) % PCI_NUM_PINS;
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Aml *pkg = aml_package(4);
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aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF));
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aml_append(pkg, aml_int(i));
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aml_append(pkg, aml_name("GSI%d", gsi));
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aml_append(pkg, aml_int(0));
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aml_append(rt_pkg, pkg);
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}
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}
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aml_append(dev, aml_name_decl("_PRT", rt_pkg));
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/* Create GSI link device */
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for (i = 0; i < PCI_NUM_PINS; i++) {
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uint32_t irqs = irq + i;
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Aml *dev_gsi = aml_device("GSI%d", i);
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aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
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aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i)));
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crs = aml_resource_template();
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aml_append(crs,
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aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
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AML_EXCLUSIVE, &irqs, 1));
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aml_append(dev_gsi, aml_name_decl("_PRS", crs));
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crs = aml_resource_template();
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aml_append(crs,
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aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
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AML_EXCLUSIVE, &irqs, 1));
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aml_append(dev_gsi, aml_name_decl("_CRS", crs));
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method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
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aml_append(dev_gsi, method);
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aml_append(dev, dev_gsi);
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}
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method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
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aml_append(method, aml_return(aml_int(base_ecam)));
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aml_append(dev, method);
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method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
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Aml *rbuf = aml_resource_template();
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aml_append(rbuf,
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aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
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nr_pcie_buses));
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aml_append(rbuf,
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aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
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base_mmio + size_mmio - 1, 0x0000, size_mmio));
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aml_append(rbuf,
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aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
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size_pio));
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if (use_highmem) {
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if (use_highmem) {
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hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
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cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO];
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hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size;
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aml_append(rbuf,
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aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
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base_mmio_high,
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base_mmio_high + size_mmio_high - 1, 0x0000,
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size_mmio_high));
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}
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}
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aml_append(method, aml_return(rbuf));
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acpi_dsdt_add_gpex(scope, &cfg);
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aml_append(dev, method);
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/* Declare an _OSC (OS Control Handoff) method */
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aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
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aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
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method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
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aml_append(method,
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aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
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/* PCI Firmware Specification 3.0
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* 4.5.1. _OSC Interface for PCI Host Bridge Devices
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* The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
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* identified by the Universal Unique IDentifier (UUID)
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* 33DB4D5B-1FF7-401C-9657-7441C03DD766
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*/
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UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
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ifctx = aml_if(aml_equal(aml_arg(0), UUID));
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aml_append(ifctx,
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aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
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aml_append(ifctx,
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aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
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aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
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aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
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/*
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* Allow OS control for all 5 features:
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* PCIeHotplug SHPCHotplug PME AER PCIeCapability.
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*/
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aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F),
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aml_name("CTRL")));
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ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
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aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08),
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aml_name("CDW1")));
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aml_append(ifctx, ifctx1);
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ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
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aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10),
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aml_name("CDW1")));
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aml_append(ifctx, ifctx1);
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aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
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aml_append(ifctx, aml_return(aml_arg(3)));
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aml_append(method, ifctx);
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elsectx = aml_else();
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aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4),
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aml_name("CDW1")));
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aml_append(elsectx, aml_return(aml_arg(3)));
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aml_append(method, elsectx);
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aml_append(dev, method);
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method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
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/* PCI Firmware Specification 3.0
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* 4.6.1. _DSM for PCI Express Slot Information
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* The UUID in _DSM in this context is
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* {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
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*/
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UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
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ifctx = aml_if(aml_equal(aml_arg(0), UUID));
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ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
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uint8_t byte_list[1] = {1};
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buf = aml_buffer(1, byte_list);
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aml_append(ifctx1, aml_return(buf));
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aml_append(ifctx, ifctx1);
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aml_append(method, ifctx);
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byte_list[0] = 0;
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buf = aml_buffer(1, byte_list);
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aml_append(method, aml_return(buf));
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aml_append(dev, method);
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Aml *dev_res0 = aml_device("%s", "RES0");
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aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
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crs = aml_resource_template();
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aml_append(crs,
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aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_ecam,
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base_ecam + size_ecam - 1, 0x0000, size_ecam));
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aml_append(dev_res0, aml_name_decl("_CRS", crs));
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aml_append(dev, dev_res0);
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aml_append(scope, dev);
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}
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}
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static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
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static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
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@ -104,6 +104,7 @@ config MICROVM
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select MC146818RTC
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select MC146818RTC
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select VIRTIO_MMIO
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select VIRTIO_MMIO
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select ACPI_HW_REDUCED
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select ACPI_HW_REDUCED
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select PCI_EXPRESS_GENERIC_BRIDGE
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config X86_IOMMU
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config X86_IOMMU
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bool
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bool
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@ -33,6 +33,8 @@
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#include "hw/boards.h"
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#include "hw/boards.h"
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#include "hw/i386/fw_cfg.h"
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#include "hw/i386/fw_cfg.h"
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#include "hw/i386/microvm.h"
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#include "hw/i386/microvm.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pcie_host.h"
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#include "hw/virtio/virtio-mmio.h"
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#include "hw/virtio/virtio-mmio.h"
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#include "acpi-common.h"
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#include "acpi-common.h"
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@ -87,6 +89,15 @@ static void acpi_dsdt_add_virtio(Aml *scope,
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}
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}
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}
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}
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static void acpi_dsdt_add_pci(Aml *scope, MicrovmMachineState *mms)
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{
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if (mms->pcie != ON_OFF_AUTO_ON) {
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return;
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}
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acpi_dsdt_add_gpex(scope, &mms->gpex);
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}
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static void
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static void
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build_dsdt_microvm(GArray *table_data, BIOSLinker *linker,
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build_dsdt_microvm(GArray *table_data, BIOSLinker *linker,
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MicrovmMachineState *mms)
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MicrovmMachineState *mms)
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@ -112,6 +123,7 @@ build_dsdt_microvm(GArray *table_data, BIOSLinker *linker,
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GED_MMIO_IRQ, AML_SYSTEM_MEMORY, GED_MMIO_BASE);
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GED_MMIO_IRQ, AML_SYSTEM_MEMORY, GED_MMIO_BASE);
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acpi_dsdt_add_power_button(sb_scope);
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acpi_dsdt_add_power_button(sb_scope);
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acpi_dsdt_add_virtio(sb_scope, mms);
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acpi_dsdt_add_virtio(sb_scope, mms);
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acpi_dsdt_add_pci(sb_scope, mms);
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aml_append(dsdt, sb_scope);
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aml_append(dsdt, sb_scope);
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/* ACPI 5.0: Table 7-209 System State Package */
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/* ACPI 5.0: Table 7-209 System State Package */
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@ -46,6 +46,7 @@
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#include "hw/virtio/virtio-mmio.h"
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#include "hw/virtio/virtio-mmio.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/generic_event_device.h"
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#include "hw/acpi/generic_event_device.h"
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#include "hw/pci-host/gpex.h"
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#include "cpu.h"
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#include "cpu.h"
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#include "elf.h"
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#include "elf.h"
|
||||||
@ -101,6 +102,55 @@ static void microvm_gsi_handler(void *opaque, int n, int level)
|
|||||||
qemu_set_irq(s->ioapic_irq[n], level);
|
qemu_set_irq(s->ioapic_irq[n], level);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void create_gpex(MicrovmMachineState *mms)
|
||||||
|
{
|
||||||
|
X86MachineState *x86ms = X86_MACHINE(mms);
|
||||||
|
MemoryRegion *mmio32_alias;
|
||||||
|
MemoryRegion *mmio64_alias;
|
||||||
|
MemoryRegion *mmio_reg;
|
||||||
|
MemoryRegion *ecam_alias;
|
||||||
|
MemoryRegion *ecam_reg;
|
||||||
|
DeviceState *dev;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
dev = qdev_new(TYPE_GPEX_HOST);
|
||||||
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
||||||
|
|
||||||
|
/* Map only the first size_ecam bytes of ECAM space */
|
||||||
|
ecam_alias = g_new0(MemoryRegion, 1);
|
||||||
|
ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
|
||||||
|
memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
|
||||||
|
ecam_reg, 0, mms->gpex.ecam.size);
|
||||||
|
memory_region_add_subregion(get_system_memory(),
|
||||||
|
mms->gpex.ecam.base, ecam_alias);
|
||||||
|
|
||||||
|
/* Map the MMIO window into system address space so as to expose
|
||||||
|
* the section of PCI MMIO space which starts at the same base address
|
||||||
|
* (ie 1:1 mapping for that part of PCI MMIO space visible through
|
||||||
|
* the window).
|
||||||
|
*/
|
||||||
|
mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
|
||||||
|
if (mms->gpex.mmio32.size) {
|
||||||
|
mmio32_alias = g_new0(MemoryRegion, 1);
|
||||||
|
memory_region_init_alias(mmio32_alias, OBJECT(dev), "pcie-mmio32", mmio_reg,
|
||||||
|
mms->gpex.mmio32.base, mms->gpex.mmio32.size);
|
||||||
|
memory_region_add_subregion(get_system_memory(),
|
||||||
|
mms->gpex.mmio32.base, mmio32_alias);
|
||||||
|
}
|
||||||
|
if (mms->gpex.mmio64.size) {
|
||||||
|
mmio64_alias = g_new0(MemoryRegion, 1);
|
||||||
|
memory_region_init_alias(mmio64_alias, OBJECT(dev), "pcie-mmio64", mmio_reg,
|
||||||
|
mms->gpex.mmio64.base, mms->gpex.mmio64.size);
|
||||||
|
memory_region_add_subregion(get_system_memory(),
|
||||||
|
mms->gpex.mmio64.base, mmio64_alias);
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < GPEX_NUM_IRQS; i++) {
|
||||||
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
|
||||||
|
x86ms->gsi[mms->gpex.irq + i]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
static void microvm_devices_init(MicrovmMachineState *mms)
|
static void microvm_devices_init(MicrovmMachineState *mms)
|
||||||
{
|
{
|
||||||
X86MachineState *x86ms = X86_MACHINE(mms);
|
X86MachineState *x86ms = X86_MACHINE(mms);
|
||||||
@ -147,6 +197,21 @@ static void microvm_devices_init(MicrovmMachineState *mms)
|
|||||||
x86ms->acpi_dev = HOTPLUG_HANDLER(dev);
|
x86ms->acpi_dev = HOTPLUG_HANDLER(dev);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (x86_machine_is_acpi_enabled(x86ms) && mms->pcie == ON_OFF_AUTO_ON) {
|
||||||
|
/* use topmost 25% of the address space available */
|
||||||
|
hwaddr phys_size = (hwaddr)1 << X86_CPU(first_cpu)->phys_bits;
|
||||||
|
if (phys_size > 0x1000000ll) {
|
||||||
|
mms->gpex.mmio64.size = phys_size / 4;
|
||||||
|
mms->gpex.mmio64.base = phys_size - mms->gpex.mmio64.size;
|
||||||
|
}
|
||||||
|
mms->gpex.mmio32.base = PCIE_MMIO_BASE;
|
||||||
|
mms->gpex.mmio32.size = PCIE_MMIO_SIZE;
|
||||||
|
mms->gpex.ecam.base = PCIE_ECAM_BASE;
|
||||||
|
mms->gpex.ecam.size = PCIE_ECAM_SIZE;
|
||||||
|
mms->gpex.irq = PCIE_IRQ_BASE;
|
||||||
|
create_gpex(mms);
|
||||||
|
}
|
||||||
|
|
||||||
if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) {
|
if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) {
|
||||||
qemu_irq *i8259;
|
qemu_irq *i8259;
|
||||||
|
|
||||||
@ -324,6 +389,9 @@ static void microvm_fix_kernel_cmdline(MachineState *machine)
|
|||||||
static void microvm_device_pre_plug_cb(HotplugHandler *hotplug_dev,
|
static void microvm_device_pre_plug_cb(HotplugHandler *hotplug_dev,
|
||||||
DeviceState *dev, Error **errp)
|
DeviceState *dev, Error **errp)
|
||||||
{
|
{
|
||||||
|
X86CPU *cpu = X86_CPU(dev);
|
||||||
|
|
||||||
|
cpu->host_phys_bits = true; /* need reliable phys-bits */
|
||||||
x86_cpu_pre_plug(hotplug_dev, dev, errp);
|
x86_cpu_pre_plug(hotplug_dev, dev, errp);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -446,6 +514,23 @@ static void microvm_machine_set_rtc(Object *obj, Visitor *v, const char *name,
|
|||||||
visit_type_OnOffAuto(v, name, &mms->rtc, errp);
|
visit_type_OnOffAuto(v, name, &mms->rtc, errp);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void microvm_machine_get_pcie(Object *obj, Visitor *v, const char *name,
|
||||||
|
void *opaque, Error **errp)
|
||||||
|
{
|
||||||
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
||||||
|
OnOffAuto pcie = mms->pcie;
|
||||||
|
|
||||||
|
visit_type_OnOffAuto(v, name, &pcie, errp);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void microvm_machine_set_pcie(Object *obj, Visitor *v, const char *name,
|
||||||
|
void *opaque, Error **errp)
|
||||||
|
{
|
||||||
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
||||||
|
|
||||||
|
visit_type_OnOffAuto(v, name, &mms->pcie, errp);
|
||||||
|
}
|
||||||
|
|
||||||
static bool microvm_machine_get_isa_serial(Object *obj, Error **errp)
|
static bool microvm_machine_get_isa_serial(Object *obj, Error **errp)
|
||||||
{
|
{
|
||||||
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
MicrovmMachineState *mms = MICROVM_MACHINE(obj);
|
||||||
@ -521,6 +606,7 @@ static void microvm_machine_initfn(Object *obj)
|
|||||||
mms->pic = ON_OFF_AUTO_AUTO;
|
mms->pic = ON_OFF_AUTO_AUTO;
|
||||||
mms->pit = ON_OFF_AUTO_AUTO;
|
mms->pit = ON_OFF_AUTO_AUTO;
|
||||||
mms->rtc = ON_OFF_AUTO_AUTO;
|
mms->rtc = ON_OFF_AUTO_AUTO;
|
||||||
|
mms->pcie = ON_OFF_AUTO_AUTO;
|
||||||
mms->isa_serial = true;
|
mms->isa_serial = true;
|
||||||
mms->option_roms = true;
|
mms->option_roms = true;
|
||||||
mms->auto_kernel_cmdline = true;
|
mms->auto_kernel_cmdline = true;
|
||||||
@ -587,6 +673,13 @@ static void microvm_class_init(ObjectClass *oc, void *data)
|
|||||||
object_class_property_set_description(oc, MICROVM_MACHINE_RTC,
|
object_class_property_set_description(oc, MICROVM_MACHINE_RTC,
|
||||||
"Enable MC146818 RTC");
|
"Enable MC146818 RTC");
|
||||||
|
|
||||||
|
object_class_property_add(oc, MICROVM_MACHINE_PCIE, "OnOffAuto",
|
||||||
|
microvm_machine_get_pcie,
|
||||||
|
microvm_machine_set_pcie,
|
||||||
|
NULL, NULL);
|
||||||
|
object_class_property_set_description(oc, MICROVM_MACHINE_PCIE,
|
||||||
|
"Enable PCIe");
|
||||||
|
|
||||||
object_class_property_add_bool(oc, MICROVM_MACHINE_ISA_SERIAL,
|
object_class_property_add_bool(oc, MICROVM_MACHINE_ISA_SERIAL,
|
||||||
microvm_machine_get_isa_serial,
|
microvm_machine_get_isa_serial,
|
||||||
microvm_machine_set_isa_serial);
|
microvm_machine_set_isa_serial);
|
||||||
|
|||||||
177
hw/pci-host/gpex-acpi.c
Normal file
177
hw/pci-host/gpex-acpi.c
Normal file
@ -0,0 +1,177 @@
|
|||||||
|
#include "qemu/osdep.h"
|
||||||
|
#include "hw/acpi/aml-build.h"
|
||||||
|
#include "hw/pci-host/gpex.h"
|
||||||
|
|
||||||
|
void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
|
||||||
|
{
|
||||||
|
int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN;
|
||||||
|
Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
|
||||||
|
int i, slot_no;
|
||||||
|
|
||||||
|
Aml *dev = aml_device("%s", "PCI0");
|
||||||
|
aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
|
||||||
|
aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
|
||||||
|
aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
|
||||||
|
aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
|
||||||
|
aml_append(dev, aml_name_decl("_UID", aml_int(0)));
|
||||||
|
aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
|
||||||
|
aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
|
||||||
|
|
||||||
|
/* Declare the PCI Routing Table. */
|
||||||
|
Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS);
|
||||||
|
for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) {
|
||||||
|
for (i = 0; i < PCI_NUM_PINS; i++) {
|
||||||
|
int gsi = (i + slot_no) % PCI_NUM_PINS;
|
||||||
|
Aml *pkg = aml_package(4);
|
||||||
|
aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF));
|
||||||
|
aml_append(pkg, aml_int(i));
|
||||||
|
aml_append(pkg, aml_name("GSI%d", gsi));
|
||||||
|
aml_append(pkg, aml_int(0));
|
||||||
|
aml_append(rt_pkg, pkg);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
aml_append(dev, aml_name_decl("_PRT", rt_pkg));
|
||||||
|
|
||||||
|
/* Create GSI link device */
|
||||||
|
for (i = 0; i < PCI_NUM_PINS; i++) {
|
||||||
|
uint32_t irqs = cfg->irq + i;
|
||||||
|
Aml *dev_gsi = aml_device("GSI%d", i);
|
||||||
|
aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
|
||||||
|
aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i)));
|
||||||
|
crs = aml_resource_template();
|
||||||
|
aml_append(crs,
|
||||||
|
aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
|
||||||
|
AML_EXCLUSIVE, &irqs, 1));
|
||||||
|
aml_append(dev_gsi, aml_name_decl("_PRS", crs));
|
||||||
|
crs = aml_resource_template();
|
||||||
|
aml_append(crs,
|
||||||
|
aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
|
||||||
|
AML_EXCLUSIVE, &irqs, 1));
|
||||||
|
aml_append(dev_gsi, aml_name_decl("_CRS", crs));
|
||||||
|
method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
|
||||||
|
aml_append(dev_gsi, method);
|
||||||
|
aml_append(dev, dev_gsi);
|
||||||
|
}
|
||||||
|
|
||||||
|
method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
|
||||||
|
aml_append(method, aml_return(aml_int(cfg->ecam.base)));
|
||||||
|
aml_append(dev, method);
|
||||||
|
|
||||||
|
Aml *rbuf = aml_resource_template();
|
||||||
|
aml_append(rbuf,
|
||||||
|
aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
|
||||||
|
0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
|
||||||
|
nr_pcie_buses));
|
||||||
|
if (cfg->mmio32.size) {
|
||||||
|
aml_append(rbuf,
|
||||||
|
aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
|
||||||
|
AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
|
||||||
|
cfg->mmio32.base,
|
||||||
|
cfg->mmio32.base + cfg->mmio32.size - 1,
|
||||||
|
0x0000,
|
||||||
|
cfg->mmio32.size));
|
||||||
|
}
|
||||||
|
if (cfg->pio.size) {
|
||||||
|
aml_append(rbuf,
|
||||||
|
aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
|
||||||
|
AML_ENTIRE_RANGE, 0x0000, 0x0000,
|
||||||
|
cfg->pio.size - 1,
|
||||||
|
cfg->pio.base,
|
||||||
|
cfg->pio.size));
|
||||||
|
}
|
||||||
|
if (cfg->mmio64.size) {
|
||||||
|
aml_append(rbuf,
|
||||||
|
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
|
||||||
|
AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
|
||||||
|
cfg->mmio64.base,
|
||||||
|
cfg->mmio64.base + cfg->mmio64.size - 1,
|
||||||
|
0x0000,
|
||||||
|
cfg->mmio64.size));
|
||||||
|
}
|
||||||
|
aml_append(dev, aml_name_decl("_CRS", rbuf));
|
||||||
|
|
||||||
|
/* Declare an _OSC (OS Control Handoff) method */
|
||||||
|
aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
|
||||||
|
aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
|
||||||
|
method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
|
||||||
|
aml_append(method,
|
||||||
|
aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
|
||||||
|
|
||||||
|
/* PCI Firmware Specification 3.0
|
||||||
|
* 4.5.1. _OSC Interface for PCI Host Bridge Devices
|
||||||
|
* The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
|
||||||
|
* identified by the Universal Unique IDentifier (UUID)
|
||||||
|
* 33DB4D5B-1FF7-401C-9657-7441C03DD766
|
||||||
|
*/
|
||||||
|
UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
|
||||||
|
ifctx = aml_if(aml_equal(aml_arg(0), UUID));
|
||||||
|
aml_append(ifctx,
|
||||||
|
aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
|
||||||
|
aml_append(ifctx,
|
||||||
|
aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
|
||||||
|
aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
|
||||||
|
aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Allow OS control for all 5 features:
|
||||||
|
* PCIeHotplug SHPCHotplug PME AER PCIeCapability.
|
||||||
|
*/
|
||||||
|
aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F),
|
||||||
|
aml_name("CTRL")));
|
||||||
|
|
||||||
|
ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
|
||||||
|
aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08),
|
||||||
|
aml_name("CDW1")));
|
||||||
|
aml_append(ifctx, ifctx1);
|
||||||
|
|
||||||
|
ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
|
||||||
|
aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10),
|
||||||
|
aml_name("CDW1")));
|
||||||
|
aml_append(ifctx, ifctx1);
|
||||||
|
|
||||||
|
aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
|
||||||
|
aml_append(ifctx, aml_return(aml_arg(3)));
|
||||||
|
aml_append(method, ifctx);
|
||||||
|
|
||||||
|
elsectx = aml_else();
|
||||||
|
aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4),
|
||||||
|
aml_name("CDW1")));
|
||||||
|
aml_append(elsectx, aml_return(aml_arg(3)));
|
||||||
|
aml_append(method, elsectx);
|
||||||
|
aml_append(dev, method);
|
||||||
|
|
||||||
|
method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
|
||||||
|
|
||||||
|
/* PCI Firmware Specification 3.0
|
||||||
|
* 4.6.1. _DSM for PCI Express Slot Information
|
||||||
|
* The UUID in _DSM in this context is
|
||||||
|
* {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
|
||||||
|
*/
|
||||||
|
UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
|
||||||
|
ifctx = aml_if(aml_equal(aml_arg(0), UUID));
|
||||||
|
ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
|
||||||
|
uint8_t byte_list[1] = {1};
|
||||||
|
buf = aml_buffer(1, byte_list);
|
||||||
|
aml_append(ifctx1, aml_return(buf));
|
||||||
|
aml_append(ifctx, ifctx1);
|
||||||
|
aml_append(method, ifctx);
|
||||||
|
|
||||||
|
byte_list[0] = 0;
|
||||||
|
buf = aml_buffer(1, byte_list);
|
||||||
|
aml_append(method, aml_return(buf));
|
||||||
|
aml_append(dev, method);
|
||||||
|
|
||||||
|
Aml *dev_res0 = aml_device("%s", "RES0");
|
||||||
|
aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
|
||||||
|
crs = aml_resource_template();
|
||||||
|
aml_append(crs,
|
||||||
|
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
|
||||||
|
AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
|
||||||
|
cfg->ecam.base,
|
||||||
|
cfg->ecam.base + cfg->ecam.size - 1,
|
||||||
|
0x0000,
|
||||||
|
cfg->ecam.size));
|
||||||
|
aml_append(dev_res0, aml_name_decl("_CRS", crs));
|
||||||
|
aml_append(dev, dev_res0);
|
||||||
|
aml_append(scope, dev);
|
||||||
|
}
|
||||||
@ -3,6 +3,7 @@ pci_ss.add(when: 'CONFIG_PAM', if_true: files('pam.c'))
|
|||||||
pci_ss.add(when: 'CONFIG_PCI_BONITO', if_true: files('bonito.c'))
|
pci_ss.add(when: 'CONFIG_PCI_BONITO', if_true: files('bonito.c'))
|
||||||
pci_ss.add(when: 'CONFIG_PCI_EXPRESS_DESIGNWARE', if_true: files('designware.c'))
|
pci_ss.add(when: 'CONFIG_PCI_EXPRESS_DESIGNWARE', if_true: files('designware.c'))
|
||||||
pci_ss.add(when: 'CONFIG_PCI_EXPRESS_GENERIC_BRIDGE', if_true: files('gpex.c'))
|
pci_ss.add(when: 'CONFIG_PCI_EXPRESS_GENERIC_BRIDGE', if_true: files('gpex.c'))
|
||||||
|
pci_ss.add(when: 'CONFIG_ACPI', if_true: files('gpex-acpi.c'))
|
||||||
pci_ss.add(when: 'CONFIG_PCI_EXPRESS_Q35', if_true: files('q35.c'))
|
pci_ss.add(when: 'CONFIG_PCI_EXPRESS_Q35', if_true: files('q35.c'))
|
||||||
pci_ss.add(when: 'CONFIG_PCI_EXPRESS_XILINX', if_true: files('xilinx-pcie.c'))
|
pci_ss.add(when: 'CONFIG_PCI_EXPRESS_XILINX', if_true: files('xilinx-pcie.c'))
|
||||||
pci_ss.add(when: 'CONFIG_PCI_I440FX', if_true: files('i440fx.c'))
|
pci_ss.add(when: 'CONFIG_PCI_I440FX', if_true: files('i440fx.c'))
|
||||||
|
|||||||
@ -18,4 +18,9 @@ typedef uint64_t hwaddr;
|
|||||||
#define HWADDR_PRIx PRIx64
|
#define HWADDR_PRIx PRIx64
|
||||||
#define HWADDR_PRIX PRIX64
|
#define HWADDR_PRIX PRIX64
|
||||||
|
|
||||||
|
typedef struct MemMapEntry {
|
||||||
|
hwaddr base;
|
||||||
|
hwaddr size;
|
||||||
|
} MemMapEntry;
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@ -111,11 +111,6 @@ typedef enum VirtGICType {
|
|||||||
VIRT_GIC_VERSION_NOSEL,
|
VIRT_GIC_VERSION_NOSEL,
|
||||||
} VirtGICType;
|
} VirtGICType;
|
||||||
|
|
||||||
typedef struct MemMapEntry {
|
|
||||||
hwaddr base;
|
|
||||||
hwaddr size;
|
|
||||||
} MemMapEntry;
|
|
||||||
|
|
||||||
struct VirtMachineClass {
|
struct VirtMachineClass {
|
||||||
MachineClass parent;
|
MachineClass parent;
|
||||||
bool disallow_affinity_adjustment;
|
bool disallow_affinity_adjustment;
|
||||||
|
|||||||
@ -25,8 +25,31 @@
|
|||||||
#include "hw/boards.h"
|
#include "hw/boards.h"
|
||||||
#include "hw/i386/x86.h"
|
#include "hw/i386/x86.h"
|
||||||
#include "hw/acpi/acpi_dev_interface.h"
|
#include "hw/acpi/acpi_dev_interface.h"
|
||||||
|
#include "hw/pci-host/gpex.h"
|
||||||
#include "qom/object.h"
|
#include "qom/object.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* IRQ | pc | microvm (acpi=on)
|
||||||
|
* --------+------------+------------------
|
||||||
|
* 0 | pit |
|
||||||
|
* 1 | kbd |
|
||||||
|
* 2 | cascade |
|
||||||
|
* 3 | serial 1 |
|
||||||
|
* 4 | serial 0 | serial
|
||||||
|
* 5 | - |
|
||||||
|
* 6 | floppy |
|
||||||
|
* 7 | parallel |
|
||||||
|
* 8 | rtc | rtc (rtc=on)
|
||||||
|
* 9 | acpi | acpi (ged)
|
||||||
|
* 10 | pci lnk |
|
||||||
|
* 11 | pci lnk |
|
||||||
|
* 12 | ps2 | pcie
|
||||||
|
* 13 | fpu | pcie
|
||||||
|
* 14 | ide 0 | pcie
|
||||||
|
* 15 | ide 1 | pcie
|
||||||
|
* 16-23 | pci gsi | virtio
|
||||||
|
*/
|
||||||
|
|
||||||
/* Platform virtio definitions */
|
/* Platform virtio definitions */
|
||||||
#define VIRTIO_MMIO_BASE 0xfeb00000
|
#define VIRTIO_MMIO_BASE 0xfeb00000
|
||||||
#define VIRTIO_NUM_TRANSPORTS 8
|
#define VIRTIO_NUM_TRANSPORTS 8
|
||||||
@ -37,10 +60,17 @@
|
|||||||
#define GED_MMIO_BASE_REGS (GED_MMIO_BASE + 0x200)
|
#define GED_MMIO_BASE_REGS (GED_MMIO_BASE + 0x200)
|
||||||
#define GED_MMIO_IRQ 9
|
#define GED_MMIO_IRQ 9
|
||||||
|
|
||||||
|
#define PCIE_MMIO_BASE 0xc0000000
|
||||||
|
#define PCIE_MMIO_SIZE 0x20000000
|
||||||
|
#define PCIE_ECAM_BASE 0xe0000000
|
||||||
|
#define PCIE_ECAM_SIZE 0x10000000
|
||||||
|
#define PCIE_IRQ_BASE 12
|
||||||
|
|
||||||
/* Machine type options */
|
/* Machine type options */
|
||||||
#define MICROVM_MACHINE_PIT "pit"
|
#define MICROVM_MACHINE_PIT "pit"
|
||||||
#define MICROVM_MACHINE_PIC "pic"
|
#define MICROVM_MACHINE_PIC "pic"
|
||||||
#define MICROVM_MACHINE_RTC "rtc"
|
#define MICROVM_MACHINE_RTC "rtc"
|
||||||
|
#define MICROVM_MACHINE_PCIE "pcie"
|
||||||
#define MICROVM_MACHINE_ISA_SERIAL "isa-serial"
|
#define MICROVM_MACHINE_ISA_SERIAL "isa-serial"
|
||||||
#define MICROVM_MACHINE_OPTION_ROMS "x-option-roms"
|
#define MICROVM_MACHINE_OPTION_ROMS "x-option-roms"
|
||||||
#define MICROVM_MACHINE_AUTO_KERNEL_CMDLINE "auto-kernel-cmdline"
|
#define MICROVM_MACHINE_AUTO_KERNEL_CMDLINE "auto-kernel-cmdline"
|
||||||
@ -58,6 +88,7 @@ struct MicrovmMachineState {
|
|||||||
OnOffAuto pic;
|
OnOffAuto pic;
|
||||||
OnOffAuto pit;
|
OnOffAuto pit;
|
||||||
OnOffAuto rtc;
|
OnOffAuto rtc;
|
||||||
|
OnOffAuto pcie;
|
||||||
bool isa_serial;
|
bool isa_serial;
|
||||||
bool option_roms;
|
bool option_roms;
|
||||||
bool auto_kernel_cmdline;
|
bool auto_kernel_cmdline;
|
||||||
@ -67,6 +98,7 @@ struct MicrovmMachineState {
|
|||||||
bool kernel_cmdline_fixed;
|
bool kernel_cmdline_fixed;
|
||||||
Notifier machine_done;
|
Notifier machine_done;
|
||||||
Notifier powerdown_req;
|
Notifier powerdown_req;
|
||||||
|
struct GPEXConfig gpex;
|
||||||
};
|
};
|
||||||
|
|
||||||
#define TYPE_MICROVM_MACHINE MACHINE_TYPE_NAME("microvm")
|
#define TYPE_MICROVM_MACHINE MACHINE_TYPE_NAME("microvm")
|
||||||
|
|||||||
@ -20,6 +20,7 @@
|
|||||||
#ifndef HW_GPEX_H
|
#ifndef HW_GPEX_H
|
||||||
#define HW_GPEX_H
|
#define HW_GPEX_H
|
||||||
|
|
||||||
|
#include "exec/hwaddr.h"
|
||||||
#include "hw/sysbus.h"
|
#include "hw/sysbus.h"
|
||||||
#include "hw/pci/pci.h"
|
#include "hw/pci/pci.h"
|
||||||
#include "hw/pci/pcie_host.h"
|
#include "hw/pci/pcie_host.h"
|
||||||
@ -52,6 +53,16 @@ struct GPEXHost {
|
|||||||
int irq_num[GPEX_NUM_IRQS];
|
int irq_num[GPEX_NUM_IRQS];
|
||||||
};
|
};
|
||||||
|
|
||||||
|
struct GPEXConfig {
|
||||||
|
MemMapEntry ecam;
|
||||||
|
MemMapEntry mmio32;
|
||||||
|
MemMapEntry mmio64;
|
||||||
|
MemMapEntry pio;
|
||||||
|
int irq;
|
||||||
|
};
|
||||||
|
|
||||||
int gpex_set_irq_num(GPEXHost *s, int index, int gsi);
|
int gpex_set_irq_num(GPEXHost *s, int index, int gsi);
|
||||||
|
|
||||||
|
void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg);
|
||||||
|
|
||||||
#endif /* HW_GPEX_H */
|
#endif /* HW_GPEX_H */
|
||||||
|
|||||||
BIN
tests/data/acpi/microvm/DSDT.pcie
Normal file
BIN
tests/data/acpi/microvm/DSDT.pcie
Normal file
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1086,20 +1086,37 @@ static void test_acpi_virt_tcg_memhp(void)
|
|||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void test_acpi_microvm_prepare(test_data *data)
|
||||||
|
{
|
||||||
|
memset(data, 0, sizeof(*data));
|
||||||
|
data->machine = "microvm";
|
||||||
|
data->required_struct_types = NULL; /* no smbios */
|
||||||
|
data->required_struct_types_len = 0;
|
||||||
|
data->blkdev = "virtio-blk-device";
|
||||||
|
}
|
||||||
|
|
||||||
static void test_acpi_microvm_tcg(void)
|
static void test_acpi_microvm_tcg(void)
|
||||||
{
|
{
|
||||||
test_data data;
|
test_data data;
|
||||||
|
|
||||||
memset(&data, 0, sizeof(data));
|
test_acpi_microvm_prepare(&data);
|
||||||
data.machine = "microvm";
|
|
||||||
data.required_struct_types = NULL; /* no smbios */
|
|
||||||
data.required_struct_types_len = 0;
|
|
||||||
data.blkdev = "virtio-blk-device";
|
|
||||||
test_acpi_one(" -machine microvm,acpi=on,rtc=off",
|
test_acpi_one(" -machine microvm,acpi=on,rtc=off",
|
||||||
&data);
|
&data);
|
||||||
free_test_data(&data);
|
free_test_data(&data);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void test_acpi_microvm_pcie_tcg(void)
|
||||||
|
{
|
||||||
|
test_data data;
|
||||||
|
|
||||||
|
test_acpi_microvm_prepare(&data);
|
||||||
|
data.variant = ".pcie";
|
||||||
|
data.tcg_only = true; /* need constant host-phys-bits */
|
||||||
|
test_acpi_one(" -machine microvm,acpi=on,rtc=off,pcie=on",
|
||||||
|
&data);
|
||||||
|
free_test_data(&data);
|
||||||
|
}
|
||||||
|
|
||||||
static void test_acpi_virt_tcg_numamem(void)
|
static void test_acpi_virt_tcg_numamem(void)
|
||||||
{
|
{
|
||||||
test_data data = {
|
test_data data = {
|
||||||
@ -1224,6 +1241,9 @@ int main(int argc, char *argv[])
|
|||||||
qtest_add_func("acpi/piix4/acpihmat", test_acpi_piix4_tcg_acpi_hmat);
|
qtest_add_func("acpi/piix4/acpihmat", test_acpi_piix4_tcg_acpi_hmat);
|
||||||
qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hmat);
|
qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hmat);
|
||||||
qtest_add_func("acpi/microvm", test_acpi_microvm_tcg);
|
qtest_add_func("acpi/microvm", test_acpi_microvm_tcg);
|
||||||
|
if (strcmp(arch, "x86_64") == 0) {
|
||||||
|
qtest_add_func("acpi/microvm/pcie", test_acpi_microvm_pcie_tcg);
|
||||||
|
}
|
||||||
} else if (strcmp(arch, "aarch64") == 0) {
|
} else if (strcmp(arch, "aarch64") == 0) {
|
||||||
qtest_add_func("acpi/virt", test_acpi_virt_tcg);
|
qtest_add_func("acpi/virt", test_acpi_virt_tcg);
|
||||||
qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem);
|
qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem);
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user