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target-ppc: add TLB_NEED_LOCAL_FLUSH flag

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Introduces bit-flag in CPUPPCState::tlb_need_flush:

  TLB_NEED_LOCAL_FLUSH (0x1) - Flush local tlb

This would indicate a pending local tlb flush (isync instructions,
interrupts, ...)

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Nikunj A Dadhania 2016-09-20 22:04:59 +05:30 committed by David Gibson
parent 7ebaf79556
commit a8a6d53e36
4 changed files with 8 additions and 7 deletions
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1
target-ppc/cpu.h
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@ -1009,6 +1009,7 @@ struct CPUPPCState {
bool tlb_dirty; /* Set to non-zero when modifying TLB */ bool tlb_dirty; /* Set to non-zero when modifying TLB */
bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */ bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
uint32_t tlb_need_flush; /* Delayed flush needed */ uint32_t tlb_need_flush; /* Delayed flush needed */
#define TLB_NEED_LOCAL_FLUSH 0x1
#endif #endif
/* Other registers */ /* Other registers */

4
target-ppc/helper_regs.h
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@ -157,9 +157,9 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
static inline void check_tlb_flush(CPUPPCState *env) static inline void check_tlb_flush(CPUPPCState *env)
{ {
CPUState *cs = CPU(ppc_env_get_cpu(env)); CPUState *cs = CPU(ppc_env_get_cpu(env));
if (env->tlb_need_flush) { if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
env->tlb_need_flush = 0;
tlb_flush(cs, 1); tlb_flush(cs, 1);
env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
} }
} }
#else #else

4
target-ppc/mmu-hash64.c
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@ -110,7 +110,7 @@ void helper_slbia(CPUPPCState *env)
* and we still don't have a tlb_flush_mask(env, n, mask) * and we still don't have a tlb_flush_mask(env, n, mask)
* in QEMU, we just invalidate all TLBs * in QEMU, we just invalidate all TLBs
*/ */
env->tlb_need_flush = 1; env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
} }
} }
} }
@ -132,7 +132,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr)
* and we still don't have a tlb_flush_mask(env, n, mask) * and we still don't have a tlb_flush_mask(env, n, mask)
* in QEMU, we just invalidate all TLBs * in QEMU, we just invalidate all TLBs
*/ */
env->tlb_need_flush = 1; env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
} }
} }

6
target-ppc/mmu_helper.c
View File

@ -1965,7 +1965,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
* we just mark the TLB to be flushed later (context synchronizing * we just mark the TLB to be flushed later (context synchronizing
* event or sync instruction on 32-bit). * event or sync instruction on 32-bit).
*/ */
env->tlb_need_flush = 1; env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
break; break;
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
case POWERPC_MMU_64B: case POWERPC_MMU_64B:
@ -1979,7 +1979,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
* and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,
* we just invalidate all TLBs * we just invalidate all TLBs
*/ */
env->tlb_need_flush = 1; env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
break; break;
#endif /* defined(TARGET_PPC64) */ #endif /* defined(TARGET_PPC64) */
default: default:
@ -2065,7 +2065,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
} }
} }
#else #else
env->tlb_need_flush = 1; env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
#endif #endif
} }
} }