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target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK

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For that move the definition from kvm.c to cpu.h

Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Message-Id: <20170509082800.10756-2-aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Aurelien Jarno 2017-05-09 10:27:58 +02:00 committed by Richard Henderson
parent 4dba4d6fef
commit a7c1fadf00
3 changed files with 4 additions and 4 deletions
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3
target/s390x/cpu.h
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@ -1078,6 +1078,9 @@ struct sysib_322 {
#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
/* SIGP order code mask corresponding to bit positions 56-63 */
#define SIGP_ORDER_MASK 0x000000ff
void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr); void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc, int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
target_ulong *raddr, int *flags, bool exc); target_ulong *raddr, int *flags, bool exc);

2
target/s390x/kvm.c
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@ -1764,8 +1764,6 @@ static int sigp_set_architecture(S390CPU *cpu, uint32_t param,
return SIGP_CC_ORDER_CODE_ACCEPTED; return SIGP_CC_ORDER_CODE_ACCEPTED;
} }
#define SIGP_ORDER_MASK 0x000000ff
static int handle_sigp(S390CPU *cpu, struct kvm_run *run, uint8_t ipa1) static int handle_sigp(S390CPU *cpu, struct kvm_run *run, uint8_t ipa1)
{ {
CPUS390XState *env = &cpu->env; CPUS390XState *env = &cpu->env;

3
target/s390x/misc_helper.c
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@ -517,8 +517,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
/* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register" /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
as parameter (input). Status (output) is always R1. */ as parameter (input). Status (output) is always R1. */
/* sigp contains the order code in bit positions 56-63, mask it here. */ switch (order_code & SIGP_ORDER_MASK) {
switch (order_code & 0xff) {
case SIGP_SET_ARCH: case SIGP_SET_ARCH:
/* switch arch */ /* switch arch */
break; break;