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target-ppc: Disentangle pte_check()
Currently support for both 32-bit and 64-bit hash MMUs share an implementation of pte_check. But there are enough differences that this means the shared function has several very ugly conditionals on "is_64b". This patch cleans things up by separating out the 64-bit version (putting it into mmu-hash64.c) and the 32-bit hash version (putting it in mmu-hash32.c). Another copy remains in mmu_helper.c, which is used for the 6xx software loaded TLB paths. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
parent
10b4652543
commit
9d7c3f4a29
@ -1,7 +1,7 @@
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obj-y += cpu-models.o
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obj-y += cpu-models.o
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obj-y += translate.o
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obj-y += translate.o
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ifeq ($(CONFIG_SOFTMMU),y)
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ifeq ($(CONFIG_SOFTMMU),y)
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obj-y += machine.o
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obj-y += machine.o mmu-hash32.o
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obj-$(TARGET_PPC64) += mmu-hash64.o
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obj-$(TARGET_PPC64) += mmu-hash64.o
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endif
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endif
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obj-$(CONFIG_KVM) += kvm.o kvm_ppc.o
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obj-$(CONFIG_KVM) += kvm.o kvm_ppc.o
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@ -1133,6 +1133,8 @@ void ppc_hw_interrupt (CPUPPCState *env);
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#if !defined(CONFIG_USER_ONLY)
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#if !defined(CONFIG_USER_ONLY)
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void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
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void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
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int pp_check(int key, int pp, int nx);
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int check_prot(int prot, int rw, int access_type);
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#endif /* !defined(CONFIG_USER_ONLY) */
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#endif /* !defined(CONFIG_USER_ONLY) */
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void ppc_store_msr (CPUPPCState *env, target_ulong value);
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void ppc_store_msr (CPUPPCState *env, target_ulong value);
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85
target-ppc/mmu-hash32.c
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85
target-ppc/mmu-hash32.c
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@ -0,0 +1,85 @@
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/*
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* PowerPC MMU, TLB and BAT emulation helpers for QEMU.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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* Copyright (c) 2013 David Gibson, IBM Corporation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "helper.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "mmu-hash32.h"
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//#define DEBUG_MMU
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#ifdef DEBUG_MMU
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# define LOG_MMU(...) qemu_log(__VA_ARGS__)
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# define LOG_MMU_STATE(env) log_cpu_state((env), 0)
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#else
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# define LOG_MMU(...) do { } while (0)
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# define LOG_MMU_STATE(...) do { } while (0)
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#endif
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#define PTE_PTEM_MASK 0x7FFFFFBF
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#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
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static inline int pte_is_valid_hash32(target_ulong pte0)
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{
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return pte0 & 0x80000000 ? 1 : 0;
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}
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int pte_check_hash32(mmu_ctx_t *ctx, target_ulong pte0,
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target_ulong pte1, int h, int rw, int type)
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{
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target_ulong ptem, mmask;
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int access, ret, pteh, ptev, pp;
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ret = -1;
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/* Check validity and table match */
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ptev = pte_is_valid_hash32(pte0);
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pteh = (pte0 >> 6) & 1;
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if (ptev && h == pteh) {
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/* Check vsid & api */
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ptem = pte0 & PTE_PTEM_MASK;
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mmask = PTE_CHECK_MASK;
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pp = pte1 & 0x00000003;
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if (ptem == ctx->ptem) {
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if (ctx->raddr != (hwaddr)-1ULL) {
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/* all matches should have equal RPN, WIMG & PP */
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if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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qemu_log("Bad RPN/WIMG/PP\n");
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return -3;
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}
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}
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/* Compute access rights */
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access = pp_check(ctx->key, pp, ctx->nx);
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/* Keep the matching PTE informations */
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ctx->raddr = pte1;
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ctx->prot = access;
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ret = check_prot(ctx->prot, rw, type);
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if (ret == 0) {
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/* Access granted */
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LOG_MMU("PTE access granted !\n");
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} else {
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/* Access right violation */
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LOG_MMU("PTE access rejected\n");
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}
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}
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}
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return ret;
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}
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12
target-ppc/mmu-hash32.h
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12
target-ppc/mmu-hash32.h
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@ -0,0 +1,12 @@
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#if !defined (__MMU_HASH32_H__)
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#define __MMU_HASH32_H__
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#ifndef CONFIG_USER_ONLY
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int pte32_is_valid(target_ulong pte0);
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int pte_check_hash32(mmu_ctx_t *ctx, target_ulong pte0,
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target_ulong pte1, int h, int rw, int type);
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#endif /* CONFIG_USER_ONLY */
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#endif /* __MMU_HASH32_H__ */
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@ -23,8 +23,17 @@
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#include "kvm_ppc.h"
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#include "kvm_ppc.h"
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#include "mmu-hash64.h"
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#include "mmu-hash64.h"
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//#define DEBUG_MMU
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//#define DEBUG_SLB
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//#define DEBUG_SLB
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#ifdef DEBUG_MMU
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# define LOG_MMU(...) qemu_log(__VA_ARGS__)
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# define LOG_MMU_STATE(env) log_cpu_state((env), 0)
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#else
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# define LOG_MMU(...) do { } while (0)
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# define LOG_MMU_STATE(...) do { } while (0)
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#endif
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#ifdef DEBUG_SLB
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#ifdef DEBUG_SLB
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# define LOG_SLB(...) qemu_log(__VA_ARGS__)
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# define LOG_SLB(...) qemu_log(__VA_ARGS__)
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#else
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#else
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@ -209,3 +218,59 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
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}
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}
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return rt;
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return rt;
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}
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}
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/*
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* 64-bit hash table MMU handling
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*/
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#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
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#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
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static inline int pte64_is_valid(target_ulong pte0)
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{
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return pte0 & 0x0000000000000001ULL ? 1 : 0;
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}
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int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,
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target_ulong pte1, int h, int rw, int type)
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{
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target_ulong ptem, mmask;
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int access, ret, pteh, ptev, pp;
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ret = -1;
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/* Check validity and table match */
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ptev = pte64_is_valid(pte0);
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pteh = (pte0 >> 1) & 1;
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if (ptev && h == pteh) {
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/* Check vsid & api */
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ptem = pte0 & PTE64_PTEM_MASK;
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mmask = PTE64_CHECK_MASK;
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pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);
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ctx->nx = (pte1 >> 2) & 1; /* No execute bit */
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ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */
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if (ptem == ctx->ptem) {
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if (ctx->raddr != (hwaddr)-1ULL) {
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/* all matches should have equal RPN, WIMG & PP */
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if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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qemu_log("Bad RPN/WIMG/PP\n");
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return -3;
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}
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}
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/* Compute access rights */
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access = pp_check(ctx->key, pp, ctx->nx);
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/* Keep the matching PTE informations */
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ctx->raddr = pte1;
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ctx->prot = access;
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ret = check_prot(ctx->prot, rw, type);
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if (ret == 0) {
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/* Access granted */
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LOG_MMU("PTE access granted !\n");
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} else {
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/* Access right violation */
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LOG_MMU("PTE access rejected\n");
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}
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}
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}
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return ret;
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}
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@ -7,6 +7,8 @@
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ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr);
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ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr);
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void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
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void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
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int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
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int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
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int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,
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target_ulong pte1, int h, int rw, int type);
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#endif
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#endif
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#endif /* CONFIG_USER_ONLY */
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#endif /* CONFIG_USER_ONLY */
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@ -21,6 +21,7 @@
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#include "sysemu/kvm.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "kvm_ppc.h"
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#include "mmu-hash64.h"
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#include "mmu-hash64.h"
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#include "mmu-hash32.h"
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//#define DEBUG_MMU
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//#define DEBUG_MMU
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//#define DEBUG_BATS
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//#define DEBUG_BATS
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@ -87,21 +88,10 @@ static inline void pte_invalidate(target_ulong *pte0)
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*pte0 &= ~0x80000000;
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*pte0 &= ~0x80000000;
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}
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}
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#if defined(TARGET_PPC64)
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static inline int pte64_is_valid(target_ulong pte0)
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{
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return pte0 & 0x0000000000000001ULL ? 1 : 0;
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}
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#endif
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#define PTE_PTEM_MASK 0x7FFFFFBF
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#define PTE_PTEM_MASK 0x7FFFFFBF
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#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
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#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
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#if defined(TARGET_PPC64)
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#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
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#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
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#endif
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static inline int pp_check(int key, int pp, int nx)
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int pp_check(int key, int pp, int nx)
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{
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{
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int access;
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int access;
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@ -142,7 +132,7 @@ static inline int pp_check(int key, int pp, int nx)
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return access;
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return access;
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}
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}
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static inline int check_prot(int prot, int rw, int access_type)
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int check_prot(int prot, int rw, int access_type)
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{
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{
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int ret;
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int ret;
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@ -169,40 +159,21 @@ static inline int check_prot(int prot, int rw, int access_type)
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return ret;
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return ret;
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}
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}
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static inline int pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
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static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0,
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target_ulong pte1, int h, int rw, int type)
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target_ulong pte1, int h, int rw, int type)
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{
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{
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target_ulong ptem, mmask;
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target_ulong ptem, mmask;
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int access, ret, pteh, ptev, pp;
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int access, ret, pteh, ptev, pp;
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ret = -1;
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ret = -1;
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/* Check validity and table match */
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/* Check validity and table match */
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#if defined(TARGET_PPC64)
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ptev = pte_is_valid(pte0);
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if (is_64b) {
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pteh = (pte0 >> 6) & 1;
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ptev = pte64_is_valid(pte0);
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pteh = (pte0 >> 1) & 1;
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} else
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#endif
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{
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ptev = pte_is_valid(pte0);
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pteh = (pte0 >> 6) & 1;
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}
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if (ptev && h == pteh) {
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if (ptev && h == pteh) {
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/* Check vsid & api */
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/* Check vsid & api */
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#if defined(TARGET_PPC64)
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ptem = pte0 & PTE_PTEM_MASK;
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if (is_64b) {
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mmask = PTE_CHECK_MASK;
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ptem = pte0 & PTE64_PTEM_MASK;
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pp = pte1 & 0x00000003;
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mmask = PTE64_CHECK_MASK;
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pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);
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ctx->nx = (pte1 >> 2) & 1; /* No execute bit */
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ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */
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} else
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#endif
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{
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ptem = pte0 & PTE_PTEM_MASK;
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mmask = PTE_CHECK_MASK;
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pp = pte1 & 0x00000003;
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}
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if (ptem == ctx->ptem) {
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if (ptem == ctx->ptem) {
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if (ctx->raddr != (hwaddr)-1ULL) {
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if (ctx->raddr != (hwaddr)-1ULL) {
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/* all matches should have equal RPN, WIMG & PP */
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/* all matches should have equal RPN, WIMG & PP */
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@ -230,20 +201,6 @@ static inline int pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
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return ret;
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return ret;
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}
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}
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static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0,
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target_ulong pte1, int h, int rw, int type)
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{
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return pte_check(ctx, 0, pte0, pte1, h, rw, type);
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}
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#if defined(TARGET_PPC64)
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static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,
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target_ulong pte1, int h, int rw, int type)
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{
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return pte_check(ctx, 1, pte0, pte1, h, rw, type);
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}
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#endif
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static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
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static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
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int ret, int rw)
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int ret, int rw)
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{
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{
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@ -381,7 +338,7 @@ static inline int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
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pte_is_valid(tlb->pte0) ? "valid" : "inval",
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pte_is_valid(tlb->pte0) ? "valid" : "inval",
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tlb->EPN, eaddr, tlb->pte1,
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tlb->EPN, eaddr, tlb->pte1,
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rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
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rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
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switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
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switch (ppc6xx_tlb_pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
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case -3:
|
case -3:
|
||||||
/* TLB inconsistency */
|
/* TLB inconsistency */
|
||||||
return -1;
|
return -1;
|
||||||
@ -590,7 +547,7 @@ static inline int find_pte2(CPUPPCState *env, mmu_ctx_t *ctx, int is_64b, int h,
|
|||||||
pte0 = ldl_phys(env->htab_base + pteg_off + (i * 8));
|
pte0 = ldl_phys(env->htab_base + pteg_off + (i * 8));
|
||||||
pte1 = ldl_phys(env->htab_base + pteg_off + (i * 8) + 4);
|
pte1 = ldl_phys(env->htab_base + pteg_off + (i * 8) + 4);
|
||||||
}
|
}
|
||||||
r = pte32_check(ctx, pte0, pte1, h, rw, type);
|
r = pte_check_hash32(ctx, pte0, pte1, h, rw, type);
|
||||||
LOG_MMU("Load pte from %08" HWADDR_PRIx " => " TARGET_FMT_lx " "
|
LOG_MMU("Load pte from %08" HWADDR_PRIx " => " TARGET_FMT_lx " "
|
||||||
TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
|
TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
|
||||||
pteg_off + (i * 8), pte0, pte1, (int)(pte0 >> 31), h,
|
pteg_off + (i * 8), pte0, pte1, (int)(pte0 >> 31), h,
|
||||||
|
Loading…
Reference in New Issue
Block a user