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target/ppc: Big-core scratch register fix

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The per-core SCRATCH0-7 registers are shared between big cores, which
was missed in the big-core implementation. It is difficult to model
well with the big-core == 2xPnvCore scheme we moved to, this fix
uses the even PnvCore to store the scrach data.

Also remove a stray log message that came in with the same patch that
introduced patch.

Fixes: c26504afd5 ("ppc/pnv: Add a big-core mode that joins two regular cores")
Cc: qemu-stable@nongnu.org
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2024-09-06 08:13:51 +10:00
parent dfaecc04c4
commit 9808ce6d5c
1 changed files with 8 additions and 1 deletions
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9
target/ppc/misc_helper.c
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@ -332,6 +332,10 @@ target_ulong helper_load_sprd(CPUPPCState *env)
PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
target_ulong sprc = env->spr[SPR_POWER_SPRC];
if (pc->big_core) {
pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1);
}
switch (sprc & 0x3e0) {
case 0: /* SCRATCH0-3 */
case 1: /* SCRATCH4-7 */
@ -368,6 +372,10 @@ void helper_store_sprd(CPUPPCState *env, target_ulong val)
PnvCore *pc = pnv_cpu_state(cpu)->pnv_core;
int nr;
if (pc->big_core) {
pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1);
}
switch (sprc & 0x3e0) {
case 0: /* SCRATCH0-3 */
case 1: /* SCRATCH4-7 */
@ -378,7 +386,6 @@ void helper_store_sprd(CPUPPCState *env, target_ulong val)
* information. Could also dump these upon checkstop.
*/
nr = (sprc >> 3) & 0x7;
qemu_log("SPRD write 0x" TARGET_FMT_lx " to SCRATCH%d\n", val, nr);
pc->scratch[nr] = val;
break;
default: