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hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
When the block is disabled, all registers are reset with the exception of the ECSPI_CONREG. It is initialized to zero when the instance is created. Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM), chapter 21.7.3: Control Register (ECSPIx_CONREG) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210129132323.30946-5-bmeng.cn@gmail.com [bmeng: add a 'common_reset' function that does most of reset operation] Signed-off-by: Bin Meng <bin.meng@windriver.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -228,15 +228,23 @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
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fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
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fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
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}
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}
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static void imx_spi_reset(DeviceState *dev)
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static void imx_spi_common_reset(IMXSPIState *s)
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{
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{
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IMXSPIState *s = IMX_SPI(dev);
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int i;
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DPRINTF("\n");
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for (i = 0; i < ARRAY_SIZE(s->regs); i++) {
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switch (i) {
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memset(s->regs, 0, sizeof(s->regs));
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case ECSPI_CONREG:
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/* CONREG is not updated on soft reset */
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s->regs[ECSPI_STATREG] = 0x00000003;
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break;
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case ECSPI_STATREG:
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s->regs[i] = 0x00000003;
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break;
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default:
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s->regs[i] = 0;
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break;
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}
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}
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imx_spi_rxfifo_reset(s);
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imx_spi_rxfifo_reset(s);
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imx_spi_txfifo_reset(s);
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imx_spi_txfifo_reset(s);
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@ -246,11 +254,19 @@ static void imx_spi_reset(DeviceState *dev)
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static void imx_spi_soft_reset(IMXSPIState *s)
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static void imx_spi_soft_reset(IMXSPIState *s)
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{
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{
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imx_spi_reset(DEVICE(s));
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imx_spi_common_reset(s);
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imx_spi_update_irq(s);
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imx_spi_update_irq(s);
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}
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}
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static void imx_spi_reset(DeviceState *dev)
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{
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IMXSPIState *s = IMX_SPI(dev);
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imx_spi_common_reset(s);
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s->regs[ECSPI_CONREG] = 0;
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}
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static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
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static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
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{
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{
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uint32_t value = 0;
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uint32_t value = 0;
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