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target/arm: Flush high bits of sve register after AdvSIMD EXT

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Writes to AdvSIMD registers flush the bits above 128.

Buglink: https://bugs.launchpad.net/bugs/1863247
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214194643.23317-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson 2020-02-14 11:46:40 -08:00 committed by Peter Maydell
parent 9e946eaba8
commit 78cedfabd5
1 changed files with 1 additions and 0 deletions
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target/arm/translate-a64.c
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@ -6895,6 +6895,7 @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_resl);
write_vec_element(s, tcg_resh, rd, 1, MO_64);
tcg_temp_free_i64(tcg_resh);
clear_vec_high(s, true, rd);
}
/* TBL/TBX