mirror of
https://github.com/qemu/qemu.git
synced 2025-08-08 08:05:17 +00:00
target/arm: Implement FMOV (general) for fp16
Adding the fp16 moves to/from general registers. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180512003217.9105-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
parent
bcc531f036
commit
68130236e3
@ -5700,6 +5700,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
|
|||||||
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
|
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
|
||||||
clear_vec_high(s, true, rd);
|
clear_vec_high(s, true, rd);
|
||||||
break;
|
break;
|
||||||
|
case 3:
|
||||||
|
/* 16 bit */
|
||||||
|
tmp = tcg_temp_new_i64();
|
||||||
|
tcg_gen_ext16u_i64(tmp, tcg_rn);
|
||||||
|
write_fp_dreg(s, rd, tmp);
|
||||||
|
tcg_temp_free_i64(tmp);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
TCGv_i64 tcg_rd = cpu_reg(s, rd);
|
TCGv_i64 tcg_rd = cpu_reg(s, rd);
|
||||||
@ -5717,6 +5726,12 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
|
|||||||
/* 64 bits from top half */
|
/* 64 bits from top half */
|
||||||
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
|
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
|
||||||
break;
|
break;
|
||||||
|
case 3:
|
||||||
|
/* 16 bit */
|
||||||
|
tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
g_assert_not_reached();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -5756,6 +5771,12 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
|
|||||||
case 0xa: /* 64 bit */
|
case 0xa: /* 64 bit */
|
||||||
case 0xd: /* 64 bit to top half of quad */
|
case 0xd: /* 64 bit to top half of quad */
|
||||||
break;
|
break;
|
||||||
|
case 0x6: /* 16-bit float, 32-bit int */
|
||||||
|
case 0xe: /* 16-bit float, 64-bit int */
|
||||||
|
if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
/* fallthru */
|
||||||
default:
|
default:
|
||||||
/* all other sf/type/rmode combinations are invalid */
|
/* all other sf/type/rmode combinations are invalid */
|
||||||
unallocated_encoding(s);
|
unallocated_encoding(s);
|
||||||
|
Loading…
Reference in New Issue
Block a user