Proxmox-Port/qemu
1
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2025-10-30 19:15:42 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

target/riscv: Add DisasExtend to gen_unary

Browse Source 
Use ctx->w for ctpopw, which is the only one that can
re-use the generic algorithm for the narrow operation.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-12-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2021-08-23 12:55:16 -07:00 committed by Alistair Francis
parent f84ed8c2df
commit 6090391505
2 changed files with 15 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
target/riscv/insn_trans/trans_rvb.c.inc
View File

@ -26,7 +26,7 @@ static void gen_clz(TCGv ret, TCGv arg1)
static bool trans_clz(DisasContext *ctx, arg_clz *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_clz);
return gen_unary(ctx, a, EXT_ZERO, gen_clz);
}
static void gen_ctz(TCGv ret, TCGv arg1)
@ -37,13 +37,13 @@ static void gen_ctz(TCGv ret, TCGv arg1)
static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_ctz);
return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
}
static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, tcg_gen_ctpop_tl);
return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
}
static bool trans_andn(DisasContext *ctx, arg_andn *a)
@ -132,13 +132,13 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, tcg_gen_ext8s_tl);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
}
static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
{
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, tcg_gen_ext16s_tl);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
}
static void gen_sbop_mask(TCGv ret, TCGv shamt)
@ -366,7 +366,6 @@ GEN_TRANS_SHADD(3)
static void gen_clzw(TCGv ret, TCGv arg1)
{
tcg_gen_ext32u_tl(ret, arg1);
tcg_gen_clzi_tl(ret, ret, 64);
tcg_gen_subi_tl(ret, ret, 32);
}
@ -375,7 +374,7 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_clzw);
return gen_unary(ctx, a, EXT_ZERO, gen_clzw);
}
static void gen_ctzw(TCGv ret, TCGv arg1)
@ -388,20 +387,15 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_ctzw);
}
static void gen_cpopw(TCGv ret, TCGv arg1)
{
tcg_gen_ext32u_tl(arg1, arg1);
tcg_gen_ctpop_tl(ret, arg1);
return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
}
static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_cpopw);
ctx->w = true;
return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
}
static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)

14
target/riscv/translate.c
View File

@ -478,17 +478,15 @@ static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
return true;
}
static bool gen_unary(DisasContext *ctx, arg_r2 *a,
void(*func)(TCGv, TCGv))
static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
void (*func)(TCGv, TCGv))
{
TCGv source = tcg_temp_new();
TCGv dest = dest_gpr(ctx, a->rd);
TCGv src1 = get_gpr(ctx, a->rs1, ext);
gen_get_gpr(ctx, source, a->rs1);
func(dest, src1);
(*func)(source, source);
gen_set_gpr(ctx, a->rd, source);
tcg_temp_free(source);
gen_set_gpr(ctx, a->rd, dest);
return true;
}