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target/arm: Convert get_phys_addr_pmsav5() to not return FSC values

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Make get_phys_addr_pmsav5() return a fault type in the ARMMMUFaultInfo
structure, which we convert to the FSC at the callsite.

Note that PMSAv5 does not define any guest-visible fault status
register, so the different "fsr" values we were previously
returning are entirely arbitrary. So we can just switch to using
the most appropriae fi->type values without worrying that we
need to special-case FaultInfo->FSC conversion for PMSAv5.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Stefano Stabellini <sstabellini@kernel.org>
Message-id: 1512503192-2239-7-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2017-12-13 17:59:25 +00:00
parent da909b2c23
commit 53a4e5c5b0
1 changed files with 13 additions and 7 deletions
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20
target/arm/helper.c
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@ -9544,7 +9544,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx, MMUAccessType access_type, ARMMMUIdx mmu_idx,
hwaddr *phys_ptr, int *prot, uint32_t *fsr) hwaddr *phys_ptr, int *prot,
ARMMMUFaultInfo *fi)
{ {
int n; int n;
uint32_t mask; uint32_t mask;
@ -9573,7 +9574,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
} }
} }
if (n < 0) { if (n < 0) {
*fsr = 2; fi->type = ARMFault_Background;
return true; return true;
} }
@ -9585,11 +9586,13 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
mask = (mask >> (n * 4)) & 0xf; mask = (mask >> (n * 4)) & 0xf;
switch (mask) { switch (mask) {
case 0: case 0:
*fsr = 1; fi->type = ARMFault_Permission;
fi->level = 1;
return true; return true;
case 1: case 1:
if (is_user) { if (is_user) {
*fsr = 1; fi->type = ARMFault_Permission;
fi->level = 1;
return true; return true;
} }
*prot = PAGE_READ | PAGE_WRITE; *prot = PAGE_READ | PAGE_WRITE;
@ -9605,7 +9608,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
break; break;
case 5: case 5:
if (is_user) { if (is_user) {
*fsr = 1; fi->type = ARMFault_Permission;
fi->level = 1;
return true; return true;
} }
*prot = PAGE_READ; *prot = PAGE_READ;
@ -9615,7 +9619,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
break; break;
default: default:
/* Bad permission. */ /* Bad permission. */
*fsr = 1; fi->type = ARMFault_Permission;
fi->level = 1;
return true; return true;
} }
*prot |= PAGE_EXEC; *prot |= PAGE_EXEC;
@ -9820,7 +9825,8 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
} else { } else {
/* Pre-v7 MPU */ /* Pre-v7 MPU */
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
phys_ptr, prot, fsr); phys_ptr, prot, fi);
*fsr = arm_fi_to_sfsc(fi);
} }
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
" mmu_idx %u -> %s (prot %c%c%c)\n", " mmu_idx %u -> %s (prot %c%c%c)\n",