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target/mips: Clean up handling of CP0 register 15

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Clean up handling of CP0 register 15.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1567009614-12438-17-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic 2019-08-28 18:26:40 +02:00
parent 35e4b54d90
commit 4466cd49e5
2 changed files with 11 additions and 10 deletions
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1
target/mips/cpu.h
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@ -367,6 +367,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG15__EBASE 1 #define CP0_REG15__EBASE 1
#define CP0_REG15__CDMMBASE 2 #define CP0_REG15__CDMMBASE 2
#define CP0_REG15__CMGCRBASE 3 #define CP0_REG15__CMGCRBASE 3
#define CP0_REG15__BEVVA 4
/* CP0 Register 16 */ /* CP0 Register 16 */
#define CP0_REG16__CONFIG 0 #define CP0_REG16__CONFIG 0
#define CP0_REG16__CONFIG1 1 #define CP0_REG16__CONFIG1 1

20
target/mips/translate.c
View File

@ -7223,17 +7223,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_15: case CP0_REGISTER_15:
switch (sel) { switch (sel) {
case 0: case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid"; register_name = "PRid";
break; break;
case 1: case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg); tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase"; register_name = "EBase";
break; break;
case 3: case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr); CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@ -7956,11 +7956,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_15: case CP0_REGISTER_15:
switch (sel) { switch (sel) {
case 0: case CP0_REG15__PRID:
/* ignored */ /* ignored */
register_name = "PRid"; register_name = "PRid";
break; break;
case 1: case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg); gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase"; register_name = "EBase";
@ -8697,16 +8697,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_15: case CP0_REGISTER_15:
switch (sel) { switch (sel) {
case 0: case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid)); gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid"; register_name = "PRid";
break; break;
case 1: case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase"; register_name = "EBase";
break; break;
case 3: case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr); CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase)); tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@ -9419,11 +9419,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case CP0_REGISTER_15: case CP0_REGISTER_15:
switch (sel) { switch (sel) {
case 0: case CP0_REG15__PRID:
/* ignored */ /* ignored */
register_name = "PRid"; register_name = "PRid";
break; break;
case 1: case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2); check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg); gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase"; register_name = "EBase";