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tcg-arm: Use qemu_getauxval

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Allow host detection on linux systems without glibc 2.16 or later.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2013-06-07 07:26:20 -07:00
parent cd629de1cf
commit 41d9ea80ac
2 changed files with 30 additions and 9 deletions
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25
include/elf.h
View File

@ -411,6 +411,31 @@ typedef struct {
#define R_SPARC_5 44 #define R_SPARC_5 44
#define R_SPARC_6 45 #define R_SPARC_6 45
/* Bits present in AT_HWCAP for ARM. */
#define HWCAP_ARM_SWP (1 << 0)
#define HWCAP_ARM_HALF (1 << 1)
#define HWCAP_ARM_THUMB (1 << 2)
#define HWCAP_ARM_26BIT (1 << 3)
#define HWCAP_ARM_FAST_MULT (1 << 4)
#define HWCAP_ARM_FPA (1 << 5)
#define HWCAP_ARM_VFP (1 << 6)
#define HWCAP_ARM_EDSP (1 << 7)
#define HWCAP_ARM_JAVA (1 << 8)
#define HWCAP_ARM_IWMMXT (1 << 9)
#define HWCAP_ARM_CRUNCH (1 << 10)
#define HWCAP_ARM_THUMBEE (1 << 11)
#define HWCAP_ARM_NEON (1 << 12)
#define HWCAP_ARM_VFPv3 (1 << 13)
#define HWCAP_ARM_VFPv3D16 (1 << 14) /* also set for VFPv4-D16 */
#define HWCAP_ARM_TLS (1 << 15)
#define HWCAP_ARM_VFPv4 (1 << 16)
#define HWCAP_ARM_IDIVA (1 << 17)
#define HWCAP_ARM_IDIVT (1 << 18)
#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT)
#define HWCAP_VFPD32 (1 << 19) /* set if VFP has 32 regs */
#define HWCAP_LPAE (1 << 20)
/* Bits present in AT_HWCAP for PowerPC. */ /* Bits present in AT_HWCAP for PowerPC. */
#define PPC_FEATURE_32 0x80000000 #define PPC_FEATURE_32 0x80000000

14
tcg/arm/tcg-target.c
View File

@ -22,6 +22,7 @@
* THE SOFTWARE. * THE SOFTWARE.
*/ */
#include "elf.h"
#include "tcg-be-ldst.h" #include "tcg-be-ldst.h"
/* The __ARM_ARCH define is provided by gcc 4.8. Construct it otherwise. */ /* The __ARM_ARCH define is provided by gcc 4.8. Construct it otherwise. */
@ -58,9 +59,6 @@ static int arm_arch = __ARM_ARCH;
#ifndef use_idiv_instructions #ifndef use_idiv_instructions
bool use_idiv_instructions; bool use_idiv_instructions;
#endif #endif
#ifdef CONFIG_GETAUXVAL
# include <sys/auxv.h>
#endif
#ifndef NDEBUG #ifndef NDEBUG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
@ -2036,22 +2034,20 @@ static const TCGTargetOpDef arm_op_defs[] = {
static void tcg_target_init(TCGContext *s) static void tcg_target_init(TCGContext *s)
{ {
#if defined(CONFIG_GETAUXVAL)
/* Only probe for the platform and capabilities if we havn't already /* Only probe for the platform and capabilities if we havn't already
determined maximum values at compile time. */ determined maximum values at compile time. */
# if !defined(use_idiv_instructions) #ifndef use_idiv_instructions
{ {
unsigned long hwcap = getauxval(AT_HWCAP); unsigned long hwcap = qemu_getauxval(AT_HWCAP);
use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0; use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
} }
# endif #endif
if (__ARM_ARCH < 7) { if (__ARM_ARCH < 7) {
const char *pl = (const char *)getauxval(AT_PLATFORM); const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') { if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
arm_arch = pl[1] - '0'; arm_arch = pl[1] - '0';
} }
} }
#endif /* GETAUXVAL */
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
tcg_regset_set32(tcg_target_call_clobber_regs, 0, tcg_regset_set32(tcg_target_call_clobber_regs, 0,