Proxmox-Port/qemu
1
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2025-08-08 08:05:17 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

target-mips: optimize load operations

Browse Source 
Only allocate t1 when needed.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2012-10-09 21:53:20 +02:00
parent 2910c6cbaa
commit 3cee3050ce
1 changed files with 12 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
target-mips/translate.c
View File

@ -1591,7 +1591,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
} }
t0 = tcg_temp_new(); t0 = tcg_temp_new();
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, base, offset); gen_base_offset_addr(ctx, t0, base, offset);
switch (opc) { switch (opc) {
@ -1614,29 +1613,35 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
break; break;
case OPC_LDL: case OPC_LDL:
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
t1 = tcg_temp_new();
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
gen_helper_1e2i(ldl, t1, t1, t0, ctx->mem_idx); gen_helper_1e2i(ldl, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt); gen_store_gpr(t1, rt);
tcg_temp_free(t1);
opn = "ldl"; opn = "ldl";
break; break;
case OPC_LDR: case OPC_LDR:
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
t1 = tcg_temp_new();
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
gen_helper_1e2i(ldr, t1, t1, t0, ctx->mem_idx); gen_helper_1e2i(ldr, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt); gen_store_gpr(t1, rt);
tcg_temp_free(t1);
opn = "ldr"; opn = "ldr";
break; break;
case OPC_LDPC: case OPC_LDPC:
tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); t1 = tcg_const_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
tcg_temp_free(t1);
tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx); tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "ldpc"; opn = "ldpc";
break; break;
#endif #endif
case OPC_LWPC: case OPC_LWPC:
tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); t1 = tcg_const_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
tcg_temp_free(t1);
tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lwpc"; opn = "lwpc";
@ -1668,16 +1673,20 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
break; break;
case OPC_LWL: case OPC_LWL:
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
t1 = tcg_temp_new();
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
gen_helper_1e2i(lwl, t1, t1, t0, ctx->mem_idx); gen_helper_1e2i(lwl, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt); gen_store_gpr(t1, rt);
tcg_temp_free(t1);
opn = "lwl"; opn = "lwl";
break; break;
case OPC_LWR: case OPC_LWR:
save_cpu_state(ctx, 1); save_cpu_state(ctx, 1);
t1 = tcg_temp_new();
gen_load_gpr(t1, rt); gen_load_gpr(t1, rt);
gen_helper_1e2i(lwr, t1, t1, t0, ctx->mem_idx); gen_helper_1e2i(lwr, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt); gen_store_gpr(t1, rt);
tcg_temp_free(t1);
opn = "lwr"; opn = "lwr";
break; break;
case OPC_LL: case OPC_LL:
@ -1690,7 +1699,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
(void)opn; /* avoid a compiler warning */ (void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
tcg_temp_free(t0); tcg_temp_free(t0);
tcg_temp_free(t1);
} }
/* Store */ /* Store */