Proxmox-Port/qemu
1
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2025-08-17 16:03:30 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

include/exec: Change cpu_mmu_index argument to CPUState

Browse Source 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-01-29 20:35:06 +10:00
parent a120d32097
commit 3b91614004
23 changed files with 65 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
accel/tcg/cputlb.c
View File

@ -1601,7 +1601,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, vaddr addr,
void *p; void *p;
(void)probe_access_internal(env_cpu(env), addr, 1, MMU_INST_FETCH, (void)probe_access_internal(env_cpu(env), addr, 1, MMU_INST_FETCH,
cpu_mmu_index(env, true), false, cpu_mmu_index(env_cpu(env), true), false,
&p, &full, 0, false); &p, &full, 0, false);
if (p == NULL) { if (p == NULL) {
return -1; return -1;
@ -2959,26 +2959,30 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, Int128 val,
uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr)
{ {
MemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(env, true)); CPUState *cs = env_cpu(env);
return do_ld1_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); MemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(cs, true));
return do_ld1_mmu(cs, addr, oi, 0, MMU_INST_FETCH);
} }
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr) uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr)
{ {
MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true)); CPUState *cs = env_cpu(env);
return do_ld2_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(cs, true));
return do_ld2_mmu(cs, addr, oi, 0, MMU_INST_FETCH);
} }
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr)
{ {
MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true)); CPUState *cs = env_cpu(env);
return do_ld4_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(cs, true));
return do_ld4_mmu(cs, addr, oi, 0, MMU_INST_FETCH);
} }
uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr)
{ {
MemOpIdx oi = make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true)); CPUState *cs = env_cpu(env);
return do_ld8_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); MemOpIdx oi = make_memop_idx(MO_TEUQ, cpu_mmu_index(cs, true));
return do_ld8_mmu(cs, addr, oi, 0, MMU_INST_FETCH);
} }
uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr,

42
accel/tcg/ldst_common.c.inc
View File

@ -354,7 +354,8 @@ void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{ {
return cpu_ldub_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
return cpu_ldub_mmuidx_ra(env, addr, mmu_index, ra);
} }
int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
@ -364,7 +365,8 @@ int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{ {
return cpu_lduw_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
return cpu_lduw_be_mmuidx_ra(env, addr, mmu_index, ra);
} }
int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
@ -374,17 +376,20 @@ int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{ {
return cpu_ldl_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
return cpu_ldl_be_mmuidx_ra(env, addr, mmu_index, ra);
} }
uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{ {
return cpu_ldq_be_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
return cpu_ldq_be_mmuidx_ra(env, addr, mmu_index, ra);
} }
uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{ {
return cpu_lduw_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
return cpu_lduw_le_mmuidx_ra(env, addr, mmu_index, ra);
} }
int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
@ -394,54 +399,63 @@ int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{ {
return cpu_ldl_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
return cpu_ldl_le_mmuidx_ra(env, addr, mmu_index, ra);
} }
uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra) uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
{ {
return cpu_ldq_le_mmuidx_ra(env, addr, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
return cpu_ldq_le_mmuidx_ra(env, addr, mmu_index, ra);
} }
void cpu_stb_data_ra(CPUArchState *env, abi_ptr addr, void cpu_stb_data_ra(CPUArchState *env, abi_ptr addr,
uint32_t val, uintptr_t ra) uint32_t val, uintptr_t ra)
{ {
cpu_stb_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
cpu_stb_mmuidx_ra(env, addr, val, mmu_index, ra);
} }
void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr, void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr,
uint32_t val, uintptr_t ra) uint32_t val, uintptr_t ra)
{ {
cpu_stw_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
cpu_stw_be_mmuidx_ra(env, addr, val, mmu_index, ra);
} }
void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr, void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr,
uint32_t val, uintptr_t ra) uint32_t val, uintptr_t ra)
{ {
cpu_stl_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
cpu_stl_be_mmuidx_ra(env, addr, val, mmu_index, ra);
} }
void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr, void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr,
uint64_t val, uintptr_t ra) uint64_t val, uintptr_t ra)
{ {
cpu_stq_be_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
cpu_stq_be_mmuidx_ra(env, addr, val, mmu_index, ra);
} }
void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr, void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr,
uint32_t val, uintptr_t ra) uint32_t val, uintptr_t ra)
{ {
cpu_stw_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
cpu_stw_le_mmuidx_ra(env, addr, val, mmu_index, ra);
} }
void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr, void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr,
uint32_t val, uintptr_t ra) uint32_t val, uintptr_t ra)
{ {
cpu_stl_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
cpu_stl_le_mmuidx_ra(env, addr, val, mmu_index, ra);
} }
void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr, void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr,
uint64_t val, uintptr_t ra) uint64_t val, uintptr_t ra)
{ {
cpu_stq_le_mmuidx_ra(env, addr, val, cpu_mmu_index(env, false), ra); int mmu_index = cpu_mmu_index(env_cpu(env), false);
cpu_stq_le_mmuidx_ra(env, addr, val, mmu_index, ra);
} }
/*--------------------------*/ /*--------------------------*/

2
include/exec/cpu-all.h
View File

@ -311,7 +311,7 @@ CPUArchState *cpu_copy(CPUArchState *env);
#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2)) #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2))
#define TLB_WATCHPOINT 0 #define TLB_WATCHPOINT 0
static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
{ {
return MMU_USER_IDX; return MMU_USER_IDX;
} }

3
include/exec/cpu-common.h
View File

@ -275,9 +275,8 @@ static inline CPUState *env_cpu(CPUArchState *env)
* The user-only version of this function is inline in cpu-all.h, * The user-only version of this function is inline in cpu-all.h,
* where it always returns MMU_USER_IDX. * where it always returns MMU_USER_IDX.
*/ */
static inline int cpu_mmu_index(CPUArchState *env, bool ifetch) static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
{ {
CPUState *cs = env_cpu(env);
int ret = cs->cc->mmu_index(cs, ifetch); int ret = cs->cc->mmu_index(cs, ifetch);
tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES); tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES);
return ret; return ret;

2
semihosting/uaccess.c
View File

@ -26,7 +26,7 @@ void *uaccess_lock_user(CPUArchState *env, target_ulong addr,
ssize_t uaccess_strlen_user(CPUArchState *env, target_ulong addr) ssize_t uaccess_strlen_user(CPUArchState *env, target_ulong addr)
{ {
int mmu_idx = cpu_mmu_index(env, false); int mmu_idx = cpu_mmu_index(env_cpu(env), false);
size_t len = 0; size_t len = 0;
while (1) { while (1) {

2
target/cris/translate.c
View File

@ -2966,7 +2966,7 @@ static void cris_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
dc->cpu = env_archcpu(env); dc->cpu = env_archcpu(env);
dc->ppc = pc_start; dc->ppc = pc_start;
dc->pc = pc_start; dc->pc = pc_start;
dc->mem_index = cpu_mmu_index(env, false); dc->mem_index = cpu_mmu_index(cs, false);
dc->flags_uptodate = 1; dc->flags_uptodate = 1;
dc->flags_x = tb_flags & X_FLAG; dc->flags_x = tb_flags & X_FLAG;
dc->cc_x_uptodate = 0; dc->cc_x_uptodate = 0;

2
target/hppa/mem_helper.c
View File

@ -646,7 +646,7 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr)
void HELPER(diag_btlb)(CPUHPPAState *env) void HELPER(diag_btlb)(CPUHPPAState *env)
{ {
unsigned int phys_page, len, slot; unsigned int phys_page, len, slot;
int mmu_idx = cpu_mmu_index(env, 0); int mmu_idx = cpu_mmu_index(env_cpu(env), 0);
uintptr_t ra = GETPC(); uintptr_t ra = GETPC();
HPPATLBEntry *btlb; HPPATLBEntry *btlb;
uint64_t virt_page; uint64_t virt_page;

8
target/hppa/op_helper.c
View File

@ -59,7 +59,7 @@ void HELPER(tcond)(CPUHPPAState *env, target_ulong cond)
static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr, static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr,
uint32_t val, uint32_t mask, uintptr_t ra) uint32_t val, uint32_t mask, uintptr_t ra)
{ {
int mmu_idx = cpu_mmu_index(env, 0); int mmu_idx = cpu_mmu_index(env_cpu(env), 0);
uint32_t old, new, cmp, *haddr; uint32_t old, new, cmp, *haddr;
void *vaddr; void *vaddr;
@ -86,7 +86,7 @@ static void atomic_store_mask64(CPUHPPAState *env, target_ulong addr,
int size, uintptr_t ra) int size, uintptr_t ra)
{ {
#ifdef CONFIG_ATOMIC64 #ifdef CONFIG_ATOMIC64
int mmu_idx = cpu_mmu_index(env, 0); int mmu_idx = cpu_mmu_index(env_cpu(env), 0);
uint64_t old, new, cmp, *haddr; uint64_t old, new, cmp, *haddr;
void *vaddr; void *vaddr;
@ -235,7 +235,7 @@ static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong val,
default: default:
/* Nothing is stored, but protection is checked and the /* Nothing is stored, but protection is checked and the
cacheline is marked dirty. */ cacheline is marked dirty. */
probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra); probe_write(env, addr, 0, cpu_mmu_index(env_cpu(env), 0), ra);
break; break;
} }
} }
@ -296,7 +296,7 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val,
default: default:
/* Nothing is stored, but protection is checked and the /* Nothing is stored, but protection is checked and the
cacheline is marked dirty. */ cacheline is marked dirty. */
probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra); probe_write(env, addr, 0, cpu_mmu_index(env_cpu(env), 0), ra);
break; break;
} }
} }

2
target/i386/tcg/translate.c
View File

@ -6955,7 +6955,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
dc->cc_op_dirty = false; dc->cc_op_dirty = false;
dc->popl_esp_hack = 0; dc->popl_esp_hack = 0;
/* select memory access functions */ /* select memory access functions */
dc->mem_index = cpu_mmu_index(env, false); dc->mem_index = cpu_mmu_index(cpu, false);
dc->cpuid_features = env->features[FEAT_1_EDX]; dc->cpuid_features = env->features[FEAT_1_EDX];
dc->cpuid_ext_features = env->features[FEAT_1_ECX]; dc->cpuid_ext_features = env->features[FEAT_1_ECX];
dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX]; dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX];

2
target/loongarch/cpu_helper.c
View File

@ -224,7 +224,7 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
int prot; int prot;
if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD,
cpu_mmu_index(env, false)) != 0) { cpu_mmu_index(cs, false)) != 0) {
return -1; return -1;
} }
return phys_addr; return phys_addr;

2
target/loongarch/tcg/tlb_helper.c
View File

@ -90,7 +90,7 @@ static void invalidate_tlb_entry(CPULoongArchState *env, int index)
uint8_t tlb_ps; uint8_t tlb_ps;
LoongArchTLB *tlb = &env->tlb[index]; LoongArchTLB *tlb = &env->tlb[index];
int mmu_idx = cpu_mmu_index(env, false); int mmu_idx = cpu_mmu_index(env_cpu(env), false);
uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V); uint8_t tlb_v0 = FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V);
uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V); uint8_t tlb_v1 = FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V);
uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); uint64_t tlb_vppn = FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN);

2
target/m68k/op_helper.c
View File

@ -811,7 +811,7 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2,
uint32_t l1, l2; uint32_t l1, l2;
uintptr_t ra = GETPC(); uintptr_t ra = GETPC();
#if defined(CONFIG_ATOMIC64) #if defined(CONFIG_ATOMIC64)
int mmu_idx = cpu_mmu_index(env, 0); int mmu_idx = cpu_mmu_index(env_cpu(env), 0);
MemOpIdx oi = make_memop_idx(MO_BEUQ, mmu_idx); MemOpIdx oi = make_memop_idx(MO_BEUQ, mmu_idx);
#endif #endif

3
target/microblaze/helper.c
View File

@ -228,10 +228,9 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
MemTxAttrs *attrs) MemTxAttrs *attrs)
{ {
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
CPUMBState *env = &cpu->env;
target_ulong vaddr, paddr = 0; target_ulong vaddr, paddr = 0;
MicroBlazeMMULookup lu; MicroBlazeMMULookup lu;
int mmu_idx = cpu_mmu_index(env, false); int mmu_idx = cpu_mmu_index(cs, false);
unsigned int hit; unsigned int hit;
/* Caller doesn't initialize */ /* Caller doesn't initialize */

2
target/microblaze/mmu.c
View File

@ -305,7 +305,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
} }
hit = mmu_translate(cpu, &lu, v & TLB_EPN_MASK, hit = mmu_translate(cpu, &lu, v & TLB_EPN_MASK,
0, cpu_mmu_index(env, false)); 0, cpu_mmu_index(env_cpu(env), false));
if (hit) { if (hit) {
env->mmu.regs[MMU_R_TLBX] = lu.idx; env->mmu.regs[MMU_R_TLBX] = lu.idx;
} else { } else {

2
target/microblaze/translate.c
View File

@ -1607,7 +1607,7 @@ static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
dc->ext_imm = dc->base.tb->cs_base; dc->ext_imm = dc->base.tb->cs_base;
dc->r0 = NULL; dc->r0 = NULL;
dc->r0_set = false; dc->r0_set = false;
dc->mem_index = cpu_mmu_index(&cpu->env, false); dc->mem_index = cpu_mmu_index(cs, false);
dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER; dc->jmp_cond = dc->tb_flags & D_FLAG ? TCG_COND_ALWAYS : TCG_COND_NEVER;
dc->jmp_dest = -1; dc->jmp_dest = -1;

2
target/nios2/translate.c
View File

@ -948,7 +948,7 @@ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
Nios2CPU *cpu = env_archcpu(env); Nios2CPU *cpu = env_archcpu(env);
int page_insns; int page_insns;
dc->mem_idx = cpu_mmu_index(env, false); dc->mem_idx = cpu_mmu_index(cs, false);
dc->cr_state = cpu->cr_state; dc->cr_state = cpu->cr_state;
dc->tb_flags = dc->base.tb->flags; dc->tb_flags = dc->base.tb->flags;
dc->eic_present = cpu->eic_present; dc->eic_present = cpu->eic_present;

2
target/openrisc/translate.c
View File

@ -1528,7 +1528,7 @@ static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
CPUOpenRISCState *env = cpu_env(cs); CPUOpenRISCState *env = cpu_env(cs);
int bound; int bound;
dc->mem_idx = cpu_mmu_index(env, false); dc->mem_idx = cpu_mmu_index(cs, false);
dc->tb_flags = dc->base.tb->flags; dc->tb_flags = dc->base.tb->flags;
dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0; dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0;
dc->cpucfgr = env->cpucfgr; dc->cpucfgr = env->cpucfgr;

2
target/sparc/cpu.h
View File

@ -755,7 +755,7 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
uint32_t flags; uint32_t flags;
*pc = env->pc; *pc = env->pc;
*cs_base = env->npc; *cs_base = env->npc;
flags = cpu_mmu_index(env, false); flags = cpu_mmu_index(env_cpu(env), false);
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
if (cpu_supervisor_mode(env)) { if (cpu_supervisor_mode(env)) {
flags |= TB_FLAG_SUPER; flags |= TB_FLAG_SUPER;

2
target/sparc/ldst_helper.c
View File

@ -690,7 +690,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */ case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
break; break;
case ASI_KERNELTXT: /* Supervisor code access */ case ASI_KERNELTXT: /* Supervisor code access */
oi = make_memop_idx(memop, cpu_mmu_index(env, true)); oi = make_memop_idx(memop, cpu_mmu_index(env_cpu(env), true));
switch (size) { switch (size) {
case 1: case 1:
ret = cpu_ldb_code_mmu(env, addr, oi, GETPC()); ret = cpu_ldb_code_mmu(env, addr, oi, GETPC());

2
target/sparc/mmu_helper.c
View File

@ -901,7 +901,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
SPARCCPU *cpu = SPARC_CPU(cs); SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env; CPUSPARCState *env = &cpu->env;
hwaddr phys_addr; hwaddr phys_addr;
int mmu_idx = cpu_mmu_index(env, false); int mmu_idx = cpu_mmu_index(cs, false);
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) { if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) {
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) { if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {

2
target/tricore/helper.c
View File

@ -48,7 +48,7 @@ hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
TriCoreCPU *cpu = TRICORE_CPU(cs); TriCoreCPU *cpu = TRICORE_CPU(cs);
hwaddr phys_addr; hwaddr phys_addr;
int prot; int prot;
int mmu_idx = cpu_mmu_index(&cpu->env, false); int mmu_idx = cpu_mmu_index(cs, false);
if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, if (get_physical_address(&cpu->env, &phys_addr, &prot, addr,
MMU_DATA_LOAD, mmu_idx)) { MMU_DATA_LOAD, mmu_idx)) {

2
target/tricore/translate.c
View File

@ -8355,7 +8355,7 @@ static void tricore_tr_init_disas_context(DisasContextBase *dcbase,
{ {
DisasContext *ctx = container_of(dcbase, DisasContext, base); DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUTriCoreState *env = cpu_env(cs); CPUTriCoreState *env = cpu_env(cs);
ctx->mem_idx = cpu_mmu_index(env, false); ctx->mem_idx = cpu_mmu_index(cs, false);
uint32_t tb_flags = (uint32_t)ctx->base.tb->flags; uint32_t tb_flags = (uint32_t)ctx->base.tb->flags;
ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);

2
target/xtensa/mmu_helper.c
View File

@ -66,7 +66,7 @@ void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
* only the side-effects (ie any MMU or other exception) * only the side-effects (ie any MMU or other exception)
*/ */
probe_access(env, vaddr, 1, MMU_INST_FETCH, probe_access(env, vaddr, 1, MMU_INST_FETCH,
cpu_mmu_index(env, true), GETPC()); cpu_mmu_index(env_cpu(env), true), GETPC());
} }
void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)