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target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ

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Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP
VRINTM and VRINTZ instructions.

Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Will Newton 2014-01-31 14:47:35 +00:00 committed by Peter Maydell
parent 43630e5853
commit 34f7b0a276
1 changed files with 39 additions and 1 deletions
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40
target-arm/translate.c
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@ -4709,9 +4709,14 @@ static const uint8_t neon_3r_sizes[] = {
#define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */ #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
#define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */ #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
#define NEON_2RM_VSHLL 38 #define NEON_2RM_VSHLL 38
#define NEON_2RM_VRINTN 40
#define NEON_2RM_VRINTX 41 #define NEON_2RM_VRINTX 41
#define NEON_2RM_VRINTA 42
#define NEON_2RM_VRINTZ 43
#define NEON_2RM_VCVT_F16_F32 44 #define NEON_2RM_VCVT_F16_F32 44
#define NEON_2RM_VRINTM 45
#define NEON_2RM_VCVT_F32_F16 46 #define NEON_2RM_VCVT_F32_F16 46
#define NEON_2RM_VRINTP 47
#define NEON_2RM_VRECPE 56 #define NEON_2RM_VRECPE 56
#define NEON_2RM_VRSQRTE 57 #define NEON_2RM_VRSQRTE 57
#define NEON_2RM_VRECPE_F 58 #define NEON_2RM_VRECPE_F 58
@ -4725,7 +4730,9 @@ static int neon_2rm_is_float_op(int op)
{ {
/* Return true if this neon 2reg-misc op is float-to-float */ /* Return true if this neon 2reg-misc op is float-to-float */
return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F || return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
op == NEON_2RM_VRINTX || op >= NEON_2RM_VRECPE_F); (op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) ||
op == NEON_2RM_VRINTM || op == NEON_2RM_VRINTP ||
op >= NEON_2RM_VRECPE_F);
} }
/* Each entry in this array has bit n set if the insn allows /* Each entry in this array has bit n set if the insn allows
@ -4769,9 +4776,14 @@ static const uint8_t neon_2rm_sizes[] = {
[NEON_2RM_VMOVN] = 0x7, [NEON_2RM_VMOVN] = 0x7,
[NEON_2RM_VQMOVN] = 0x7, [NEON_2RM_VQMOVN] = 0x7,
[NEON_2RM_VSHLL] = 0x7, [NEON_2RM_VSHLL] = 0x7,
[NEON_2RM_VRINTN] = 0x4,
[NEON_2RM_VRINTX] = 0x4, [NEON_2RM_VRINTX] = 0x4,
[NEON_2RM_VRINTA] = 0x4,
[NEON_2RM_VRINTZ] = 0x4,
[NEON_2RM_VCVT_F16_F32] = 0x2, [NEON_2RM_VCVT_F16_F32] = 0x2,
[NEON_2RM_VRINTM] = 0x4,
[NEON_2RM_VCVT_F32_F16] = 0x2, [NEON_2RM_VCVT_F32_F16] = 0x2,
[NEON_2RM_VRINTP] = 0x4,
[NEON_2RM_VRECPE] = 0x4, [NEON_2RM_VRECPE] = 0x4,
[NEON_2RM_VRSQRTE] = 0x4, [NEON_2RM_VRSQRTE] = 0x4,
[NEON_2RM_VRECPE_F] = 0x4, [NEON_2RM_VRECPE_F] = 0x4,
@ -6482,6 +6494,32 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
} }
neon_store_reg(rm, pass, tmp2); neon_store_reg(rm, pass, tmp2);
break; break;
case NEON_2RM_VRINTN:
case NEON_2RM_VRINTA:
case NEON_2RM_VRINTM:
case NEON_2RM_VRINTP:
case NEON_2RM_VRINTZ:
{
TCGv_i32 tcg_rmode;
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
int rmode;
if (op == NEON_2RM_VRINTZ) {
rmode = FPROUNDING_ZERO;
} else {
rmode = fp_decode_rm[((op & 0x6) >> 1) ^ 1];
}
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
cpu_env);
gen_helper_rints(cpu_F0s, cpu_F0s, fpstatus);
gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
cpu_env);
tcg_temp_free_ptr(fpstatus);
tcg_temp_free_i32(tcg_rmode);
break;
}
case NEON_2RM_VRINTX: case NEON_2RM_VRINTX:
{ {
TCGv_ptr fpstatus = get_fpstatus_ptr(1); TCGv_ptr fpstatus = get_fpstatus_ptr(1);