Proxmox-Port/qemu
1
0
Fork 0
mirror of https://github.com/qemu/qemu.git synced 2025-08-08 08:05:17 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

target-ppc: consolidate store conditional

Browse Source 
Use tcg_gen_qemu_st store conditional instructions.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Nikunj A Dadhania 2016-09-12 12:11:38 +05:30 committed by David Gibson
parent aa2008af0c
commit 2391b35773
1 changed files with 22 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
target-ppc/translate.c
View File

@ -3076,19 +3076,19 @@ LARX(lwarx, DEF_MEMOP(MO_UL))
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
static void gen_conditional_store(DisasContext *ctx, TCGv EA, static void gen_conditional_store(DisasContext *ctx, TCGv EA,
int reg, int size) int reg, int memop)
{ {
TCGv t0 = tcg_temp_new(); TCGv t0 = tcg_temp_new();
tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
tcg_gen_movi_tl(t0, (size << 5) | reg); tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
tcg_temp_free(t0); tcg_temp_free(t0);
gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
} }
#else #else
static void gen_conditional_store(DisasContext *ctx, TCGv EA, static void gen_conditional_store(DisasContext *ctx, TCGv EA,
int reg, int size) int reg, int memop)
{ {
TCGLabel *l1; TCGLabel *l1;
@ -3096,44 +3096,36 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA,
l1 = gen_new_label(); l1 = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
#if defined(TARGET_PPC64) tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop);
if (size == 8) {
gen_qemu_st64_i64(ctx, cpu_gpr[reg], EA);
} else
#endif
if (size == 4) {
gen_qemu_st32(ctx, cpu_gpr[reg], EA);
} else if (size == 2) {
gen_qemu_st16(ctx, cpu_gpr[reg], EA);
} else {
gen_qemu_st8(ctx, cpu_gpr[reg], EA);
}
gen_set_label(l1); gen_set_label(l1);
tcg_gen_movi_tl(cpu_reserve, -1); tcg_gen_movi_tl(cpu_reserve, -1);
} }
#endif #endif
#define STCX(name, len) \ #define STCX(name, memop) \
static void gen_##name(DisasContext *ctx) \ static void gen_##name(DisasContext *ctx) \
{ \ { \
TCGv t0; \ TCGv t0; \
gen_set_access_type(ctx, ACCESS_RES); \ int len = MEMOP_GET_SIZE(memop); \
t0 = tcg_temp_local_new(); \ gen_set_access_type(ctx, ACCESS_RES); \
gen_addr_reg_index(ctx, t0); \ t0 = tcg_temp_local_new(); \
if (len > 1) { \ gen_addr_reg_index(ctx, t0); \
gen_check_align(ctx, t0, (len)-1); \ if (len > 1) { \
} \ gen_check_align(ctx, t0, (len) - 1); \
gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \ } \
tcg_temp_free(t0); \ gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
tcg_temp_free(t0); \
} }
STCX(stbcx_, 1); STCX(stbcx_, DEF_MEMOP(MO_UB))
STCX(sthcx_, 2); STCX(sthcx_, DEF_MEMOP(MO_UW))
STCX(stwcx_, 4); STCX(stwcx_, DEF_MEMOP(MO_UL))
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
/* ldarx */ /* ldarx */
LARX(ldarx, DEF_MEMOP(MO_Q)) LARX(ldarx, DEF_MEMOP(MO_Q))
/* stdcx. */
STCX(stdcx_, DEF_MEMOP(MO_Q))
/* lqarx */ /* lqarx */
static void gen_lqarx(DisasContext *ctx) static void gen_lqarx(DisasContext *ctx)
@ -3216,8 +3208,6 @@ static void gen_stqcx_(DisasContext *ctx)
tcg_temp_free(EA); tcg_temp_free(EA);
} }
/* stdcx. */
STCX(stdcx_, 8);
#endif /* defined(TARGET_PPC64) */ #endif /* defined(TARGET_PPC64) */
/* sync */ /* sync */