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target-mips: do not save CPU state when using retranslation

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When the CPU state after a possible retranslation is going to be handled
through code retranslation, we don't need to save the CPU state before.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2012-10-28 15:55:47 +01:00
parent 4636401d99
commit 1e0e239a89
1 changed files with 0 additions and 20 deletions
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20
target-mips/translate.c
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@ -1626,13 +1626,11 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
switch (opc) { switch (opc) {
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_LWU: case OPC_LWU:
save_cpu_state(ctx, 0);
op_ld_lwu(t0, t0, ctx); op_ld_lwu(t0, t0, ctx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lwu"; opn = "lwu";
break; break;
case OPC_LD: case OPC_LD:
save_cpu_state(ctx, 0);
op_ld_ld(t0, t0, ctx); op_ld_ld(t0, t0, ctx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "ld"; opn = "ld";
@ -1658,7 +1656,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
opn = "ldr"; opn = "ldr";
break; break;
case OPC_LDPC: case OPC_LDPC:
save_cpu_state(ctx, 0);
tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
op_ld_ld(t0, t0, ctx); op_ld_ld(t0, t0, ctx);
@ -1667,7 +1664,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
break; break;
#endif #endif
case OPC_LWPC: case OPC_LWPC:
save_cpu_state(ctx, 0);
tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1); gen_op_addr_add(ctx, t0, t0, t1);
op_ld_lw(t0, t0, ctx); op_ld_lw(t0, t0, ctx);
@ -1675,31 +1671,26 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
opn = "lwpc"; opn = "lwpc";
break; break;
case OPC_LW: case OPC_LW:
save_cpu_state(ctx, 0);
op_ld_lw(t0, t0, ctx); op_ld_lw(t0, t0, ctx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lw"; opn = "lw";
break; break;
case OPC_LH: case OPC_LH:
save_cpu_state(ctx, 0);
op_ld_lh(t0, t0, ctx); op_ld_lh(t0, t0, ctx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lh"; opn = "lh";
break; break;
case OPC_LHU: case OPC_LHU:
save_cpu_state(ctx, 0);
op_ld_lhu(t0, t0, ctx); op_ld_lhu(t0, t0, ctx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lhu"; opn = "lhu";
break; break;
case OPC_LB: case OPC_LB:
save_cpu_state(ctx, 0);
op_ld_lb(t0, t0, ctx); op_ld_lb(t0, t0, ctx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lb"; opn = "lb";
break; break;
case OPC_LBU: case OPC_LBU:
save_cpu_state(ctx, 0);
op_ld_lbu(t0, t0, ctx); op_ld_lbu(t0, t0, ctx);
gen_store_gpr(t0, rt); gen_store_gpr(t0, rt);
opn = "lbu"; opn = "lbu";
@ -1744,7 +1735,6 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
switch (opc) { switch (opc) {
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_SD: case OPC_SD:
save_cpu_state(ctx, 0);
op_st_sd(t1, t0, ctx); op_st_sd(t1, t0, ctx);
opn = "sd"; opn = "sd";
break; break;
@ -1760,17 +1750,14 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
break; break;
#endif #endif
case OPC_SW: case OPC_SW:
save_cpu_state(ctx, 0);
op_st_sw(t1, t0, ctx); op_st_sw(t1, t0, ctx);
opn = "sw"; opn = "sw";
break; break;
case OPC_SH: case OPC_SH:
save_cpu_state(ctx, 0);
op_st_sh(t1, t0, ctx); op_st_sh(t1, t0, ctx);
opn = "sh"; opn = "sh";
break; break;
case OPC_SB: case OPC_SB:
save_cpu_state(ctx, 0);
op_st_sb(t1, t0, ctx); op_st_sb(t1, t0, ctx);
opn = "sb"; opn = "sb";
break; break;
@ -8691,7 +8678,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
} }
/* Don't do NOP if destination is zero: we must perform the actual /* Don't do NOP if destination is zero: we must perform the actual
memory access. */ memory access. */
save_cpu_state(ctx, 0);
switch (opc) { switch (opc) {
case OPC_LWXC1: case OPC_LWXC1:
check_cop1x(ctx); check_cop1x(ctx);
@ -10964,7 +10950,6 @@ static void gen_ldxs (DisasContext *ctx, int base, int index, int rd)
gen_op_addr_add(ctx, t0, t1, t0); gen_op_addr_add(ctx, t0, t1, t0);
} }
save_cpu_state(ctx, 0);
op_ld_lw(t1, t0, ctx); op_ld_lw(t1, t0, ctx);
gen_store_gpr(t1, rd); gen_store_gpr(t1, rd);
@ -10994,7 +10979,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
generate_exception(ctx, EXCP_RI); generate_exception(ctx, EXCP_RI);
return; return;
} }
save_cpu_state(ctx, 0);
op_ld_lw(t1, t0, ctx); op_ld_lw(t1, t0, ctx);
gen_store_gpr(t1, rd); gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 4); tcg_gen_movi_tl(t1, 4);
@ -11004,7 +10988,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
opn = "lwp"; opn = "lwp";
break; break;
case SWP: case SWP:
save_cpu_state(ctx, 0);
gen_load_gpr(t1, rd); gen_load_gpr(t1, rd);
op_st_sw(t1, t0, ctx); op_st_sw(t1, t0, ctx);
tcg_gen_movi_tl(t1, 4); tcg_gen_movi_tl(t1, 4);
@ -11019,7 +11002,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
generate_exception(ctx, EXCP_RI); generate_exception(ctx, EXCP_RI);
return; return;
} }
save_cpu_state(ctx, 0);
op_ld_ld(t1, t0, ctx); op_ld_ld(t1, t0, ctx);
gen_store_gpr(t1, rd); gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 8); tcg_gen_movi_tl(t1, 8);
@ -11029,7 +11011,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd,
opn = "ldp"; opn = "ldp";
break; break;
case SDP: case SDP:
save_cpu_state(ctx, 0);
gen_load_gpr(t1, rd); gen_load_gpr(t1, rd);
op_st_sd(t1, t0, ctx); op_st_sd(t1, t0, ctx);
tcg_gen_movi_tl(t1, 8); tcg_gen_movi_tl(t1, 8);
@ -12671,7 +12652,6 @@ static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]); gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]);
} }
save_cpu_state(ctx, 0);
switch (opc) { switch (opc) {
case OPC_LBUX: case OPC_LBUX:
op_ld_lbu(t0, t0, ctx); op_ld_lbu(t0, t0, ctx);