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target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for SVE2p1

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250704142112.1018902-86-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2025-07-04 08:20:48 -06:00 committed by Peter Maydell
parent 5b334d17e6
commit 1de7ecfc12
4 changed files with 148 additions and 27 deletions
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49
target/arm/tcg/helper-sve.h
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@ -1077,6 +1077,55 @@ DEF_HELPER_FLAGS_4(sve_ah_fminv_s, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_4(sve_ah_fminv_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve_ah_fminv_d, TCG_CALL_NO_RWG,
i64, ptr, ptr, fpst, i32) i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_faddqv_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_faddqv_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_faddqv_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_fmaxnmqv_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_fmaxnmqv_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_fmaxnmqv_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_fminnmqv_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_fminnmqv_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_fminnmqv_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_fmaxqv_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_fmaxqv_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_fmaxqv_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_fminqv_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_fminqv_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_fminqv_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_ah_fmaxqv_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_ah_fmaxqv_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_ah_fmaxqv_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_ah_fminqv_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_ah_fminqv_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve2p1_ah_fminqv_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fadda_h, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fadda_h, TCG_CALL_NO_RWG,
i64, i64, ptr, ptr, fpst, i32) i64, i64, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG,

8
target/arm/tcg/sve.decode
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@ -1036,6 +1036,14 @@ FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn
FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn
FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn
### SVE FP recursive reduction (quadwords)
FADDQV 01100100 .. 010 000 101 ... ..... ..... @rd_pg_rn
FMAXNMQV 01100100 .. 010 100 101 ... ..... ..... @rd_pg_rn
FMINNMQV 01100100 .. 010 101 101 ... ..... ..... @rd_pg_rn
FMAXQV 01100100 .. 010 110 101 ... ..... ..... @rd_pg_rn
FMINQV 01100100 .. 010 111 101 ... ..... ..... @rd_pg_rn
## SVE Floating Point Unary Operations - Unpredicated Group ## SVE Floating Point Unary Operations - Unpredicated Group
FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn

70
target/arm/tcg/sve_helper.c
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@ -4361,19 +4361,20 @@ uint32_t HELPER(sve_whilecg)(void *vd, uint32_t count, uint32_t pred_desc)
* The recursion is bounded to depth 7 (128 fp16 elements), so there's * The recursion is bounded to depth 7 (128 fp16 elements), so there's
* little to gain with a more complex non-recursive form. * little to gain with a more complex non-recursive form.
*/ */
#define DO_REDUCE(NAME, TYPE, H, FUNC, IDENT) \ #define DO_REDUCE(NAME, SUF, TYPE, H, FUNC, IDENT) \
static TYPE NAME##_reduce(TYPE *data, float_status *status, uintptr_t n) \ static TYPE FUNC##_reduce(TYPE *data, float_status *status, uintptr_t n) \
{ \ { \
if (n == 1) { \ if (n == 1) { \
return *data; \ return *data; \
} else { \ } else { \
uintptr_t half = n / 2; \ uintptr_t half = n / 2; \
TYPE lo = NAME##_reduce(data, status, half); \ TYPE lo = FUNC##_reduce(data, status, half); \
TYPE hi = NAME##_reduce(data + half, status, half); \ TYPE hi = FUNC##_reduce(data + half, status, half); \
return FUNC(lo, hi, status); \ return FUNC(lo, hi, status); \
} \ } \
} \ } \
uint64_t HELPER(NAME)(void *vn, void *vg, float_status *s, uint32_t desc) \ uint64_t helper_sve_##NAME##v_##SUF(void *vn, void *vg, \
float_status *s, uint32_t desc) \
{ \ { \
uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_data(desc); \ uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_data(desc); \
TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \ TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \
@ -4388,39 +4389,54 @@ uint64_t HELPER(NAME)(void *vn, void *vg, float_status *s, uint32_t desc) \
for (; i < maxsz; i += sizeof(TYPE)) { \ for (; i < maxsz; i += sizeof(TYPE)) { \
*(TYPE *)((void *)data + i) = IDENT; \ *(TYPE *)((void *)data + i) = IDENT; \
} \ } \
return NAME##_reduce(data, s, maxsz / sizeof(TYPE)); \ return FUNC##_reduce(data, s, maxsz / sizeof(TYPE)); \
} \
void helper_sve2p1_##NAME##qv_##SUF(void *vd, void *vn, void *vg, \
float_status *status, uint32_t desc) \
{ \
unsigned oprsz = simd_oprsz(desc), segments = oprsz / 16; \
for (unsigned e = 0; e < 16; e += sizeof(TYPE)) { \
TYPE data[ARM_MAX_VQ]; \
for (unsigned s = 0; s < segments; s++) { \
uint16_t pg = *(uint16_t *)(vg + H1_2(s * 2)); \
TYPE nn = *(TYPE *)(vn + H(s * 16 + H(e))); \
data[s] = (pg >> e) & 1 ? nn : IDENT; \
} \
*(TYPE *)(vd + H(e)) = FUNC##_reduce(data, status, segments); \
} \
clear_tail(vd, 16, simd_maxsz(desc)); \
} }
DO_REDUCE(sve_faddv_h, float16, H1_2, float16_add, float16_zero) DO_REDUCE(fadd,h, float16, H1_2, float16_add, float16_zero)
DO_REDUCE(sve_faddv_s, float32, H1_4, float32_add, float32_zero) DO_REDUCE(fadd,s, float32, H1_4, float32_add, float32_zero)
DO_REDUCE(sve_faddv_d, float64, H1_8, float64_add, float64_zero) DO_REDUCE(fadd,d, float64, H1_8, float64_add, float64_zero)
/* Identity is floatN_default_nan, without the function call. */ /* Identity is floatN_default_nan, without the function call. */
DO_REDUCE(sve_fminnmv_h, float16, H1_2, float16_minnum, 0x7E00) DO_REDUCE(fminnm,h, float16, H1_2, float16_minnum, 0x7E00)
DO_REDUCE(sve_fminnmv_s, float32, H1_4, float32_minnum, 0x7FC00000) DO_REDUCE(fminnm,s, float32, H1_4, float32_minnum, 0x7FC00000)
DO_REDUCE(sve_fminnmv_d, float64, H1_8, float64_minnum, 0x7FF8000000000000ULL) DO_REDUCE(fminnm,d, float64, H1_8, float64_minnum, 0x7FF8000000000000ULL)
DO_REDUCE(sve_fmaxnmv_h, float16, H1_2, float16_maxnum, 0x7E00) DO_REDUCE(fmaxnm,h, float16, H1_2, float16_maxnum, 0x7E00)
DO_REDUCE(sve_fmaxnmv_s, float32, H1_4, float32_maxnum, 0x7FC00000) DO_REDUCE(fmaxnm,s, float32, H1_4, float32_maxnum, 0x7FC00000)
DO_REDUCE(sve_fmaxnmv_d, float64, H1_8, float64_maxnum, 0x7FF8000000000000ULL) DO_REDUCE(fmaxnm,d, float64, H1_8, float64_maxnum, 0x7FF8000000000000ULL)
DO_REDUCE(sve_fminv_h, float16, H1_2, float16_min, float16_infinity) DO_REDUCE(fmin,h, float16, H1_2, float16_min, float16_infinity)
DO_REDUCE(sve_fminv_s, float32, H1_4, float32_min, float32_infinity) DO_REDUCE(fmin,s, float32, H1_4, float32_min, float32_infinity)
DO_REDUCE(sve_fminv_d, float64, H1_8, float64_min, float64_infinity) DO_REDUCE(fmin,d, float64, H1_8, float64_min, float64_infinity)
DO_REDUCE(sve_fmaxv_h, float16, H1_2, float16_max, float16_chs(float16_infinity)) DO_REDUCE(fmax,h, float16, H1_2, float16_max, float16_chs(float16_infinity))
DO_REDUCE(sve_fmaxv_s, float32, H1_4, float32_max, float32_chs(float32_infinity)) DO_REDUCE(fmax,s, float32, H1_4, float32_max, float32_chs(float32_infinity))
DO_REDUCE(sve_fmaxv_d, float64, H1_8, float64_max, float64_chs(float64_infinity)) DO_REDUCE(fmax,d, float64, H1_8, float64_max, float64_chs(float64_infinity))
DO_REDUCE(sve_ah_fminv_h, float16, H1_2, helper_vfp_ah_minh, float16_infinity) DO_REDUCE(ah_fmin,h, float16, H1_2, helper_vfp_ah_minh, float16_infinity)
DO_REDUCE(sve_ah_fminv_s, float32, H1_4, helper_vfp_ah_mins, float32_infinity) DO_REDUCE(ah_fmin,s, float32, H1_4, helper_vfp_ah_mins, float32_infinity)
DO_REDUCE(sve_ah_fminv_d, float64, H1_8, helper_vfp_ah_mind, float64_infinity) DO_REDUCE(ah_fmin,d, float64, H1_8, helper_vfp_ah_mind, float64_infinity)
DO_REDUCE(sve_ah_fmaxv_h, float16, H1_2, helper_vfp_ah_maxh, DO_REDUCE(ah_fmax,h, float16, H1_2, helper_vfp_ah_maxh,
float16_chs(float16_infinity)) float16_chs(float16_infinity))
DO_REDUCE(sve_ah_fmaxv_s, float32, H1_4, helper_vfp_ah_maxs, DO_REDUCE(ah_fmax,s, float32, H1_4, helper_vfp_ah_maxs,
float32_chs(float32_infinity)) float32_chs(float32_infinity))
DO_REDUCE(sve_ah_fmaxv_d, float64, H1_8, helper_vfp_ah_maxd, DO_REDUCE(ah_fmax,d, float64, H1_8, helper_vfp_ah_maxd,
float64_chs(float64_infinity)) float64_chs(float64_infinity))
#undef DO_REDUCE #undef DO_REDUCE

48
target/arm/tcg/translate-sve.c
View File

@ -3743,6 +3743,54 @@ DO_VPZ_AH(FMAXV, fmaxv)
#undef DO_VPZ #undef DO_VPZ
static gen_helper_gvec_3_ptr * const faddqv_fns[4] = {
NULL, gen_helper_sve2p1_faddqv_h,
gen_helper_sve2p1_faddqv_s, gen_helper_sve2p1_faddqv_d,
};
TRANS_FEAT(FADDQV, aa64_sme2p1_or_sve2p1, gen_gvec_fpst_arg_zpz,
faddqv_fns[a->esz], a, 0,
a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
static gen_helper_gvec_3_ptr * const fmaxnmqv_fns[4] = {
NULL, gen_helper_sve2p1_fmaxnmqv_h,
gen_helper_sve2p1_fmaxnmqv_s, gen_helper_sve2p1_fmaxnmqv_d,
};
TRANS_FEAT(FMAXNMQV, aa64_sme2p1_or_sve2p1, gen_gvec_fpst_arg_zpz,
fmaxnmqv_fns[a->esz], a, 0,
a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
static gen_helper_gvec_3_ptr * const fminnmqv_fns[4] = {
NULL, gen_helper_sve2p1_fminnmqv_h,
gen_helper_sve2p1_fminnmqv_s, gen_helper_sve2p1_fminnmqv_d,
};
TRANS_FEAT(FMINNMQV, aa64_sme2p1_or_sve2p1, gen_gvec_fpst_arg_zpz,
fminnmqv_fns[a->esz], a, 0,
a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
static gen_helper_gvec_3_ptr * const fmaxqv_fns[4] = {
NULL, gen_helper_sve2p1_fmaxqv_h,
gen_helper_sve2p1_fmaxqv_s, gen_helper_sve2p1_fmaxqv_d,
};
static gen_helper_gvec_3_ptr * const fmaxqv_ah_fns[4] = {
NULL, gen_helper_sve2p1_ah_fmaxqv_h,
gen_helper_sve2p1_ah_fmaxqv_s, gen_helper_sve2p1_ah_fmaxqv_d,
};
TRANS_FEAT(FMAXQV, aa64_sme2p1_or_sve2p1, gen_gvec_fpst_arg_zpz,
(s->fpcr_ah ? fmaxqv_fns : fmaxqv_ah_fns)[a->esz], a, 0,
a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
static gen_helper_gvec_3_ptr * const fminqv_fns[4] = {
NULL, gen_helper_sve2p1_fminqv_h,
gen_helper_sve2p1_fminqv_s, gen_helper_sve2p1_fminqv_d,
};
static gen_helper_gvec_3_ptr * const fminqv_ah_fns[4] = {
NULL, gen_helper_sve2p1_ah_fminqv_h,
gen_helper_sve2p1_ah_fminqv_s, gen_helper_sve2p1_ah_fminqv_d,
};
TRANS_FEAT(FMINQV, aa64_sme2p1_or_sve2p1, gen_gvec_fpst_arg_zpz,
(s->fpcr_ah ? fminqv_fns : fminqv_ah_fns)[a->esz], a, 0,
a->esz == MO_16 ? FPST_A64_F16 : FPST_A64)
/* /*
*** SVE Floating Point Unary Operations - Unpredicated Group *** SVE Floating Point Unary Operations - Unpredicated Group
*/ */