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sh7750: convert cache and tlb to memory API

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Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Benoît Canet 2011-11-17 14:22:59 +01:00 committed by Avi Kivity
parent 382863e2c6
commit 1a4004c772
1 changed files with 22 additions and 21 deletions
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43
hw/sh7750.c
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@ -42,6 +42,7 @@ typedef struct SH7750State {
MemoryRegion iomem_ff8; MemoryRegion iomem_ff8;
MemoryRegion iomem_1fc; MemoryRegion iomem_1fc;
MemoryRegion iomem_ffc; MemoryRegion iomem_ffc;
MemoryRegion mmct_iomem;
/* CPU */ /* CPU */
CPUSH4State *cpu; CPUSH4State *cpu;
/* Peripheral frequency in Hz */ /* Peripheral frequency in Hz */
@ -623,18 +624,23 @@ static struct intc_group groups_irl[] = {
#define MM_UTLB_DATA (7) #define MM_UTLB_DATA (7)
#define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24) #define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24)
static uint32_t invalid_read(void *opaque, target_phys_addr_t addr) static uint64_t invalid_read(void *opaque, target_phys_addr_t addr)
{ {
abort(); abort();
return 0; return 0;
} }
static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr) static uint64_t sh7750_mmct_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
SH7750State *s = opaque; SH7750State *s = opaque;
uint32_t ret = 0; uint32_t ret = 0;
if (size != 4) {
return invalid_read(opaque, addr);
}
switch (MM_REGION_TYPE(addr)) { switch (MM_REGION_TYPE(addr)) {
case MM_ICACHE_ADDR: case MM_ICACHE_ADDR:
case MM_ICACHE_DATA: case MM_ICACHE_DATA:
@ -664,16 +670,20 @@ static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
} }
static void invalid_write(void *opaque, target_phys_addr_t addr, static void invalid_write(void *opaque, target_phys_addr_t addr,
uint32_t mem_value) uint64_t mem_value)
{ {
abort(); abort();
} }
static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr, static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr,
uint32_t mem_value) uint64_t mem_value, unsigned size)
{ {
SH7750State *s = opaque; SH7750State *s = opaque;
if (size != 4) {
invalid_write(opaque, addr, mem_value);
}
switch (MM_REGION_TYPE(addr)) { switch (MM_REGION_TYPE(addr)) {
case MM_ICACHE_ADDR: case MM_ICACHE_ADDR:
case MM_ICACHE_DATA: case MM_ICACHE_DATA:
@ -702,22 +712,15 @@ static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
} }
} }
static CPUReadMemoryFunc * const sh7750_mmct_read[] = { static const struct MemoryRegionOps sh7750_mmct_ops = {
invalid_read, .read = sh7750_mmct_read,
invalid_read, .write = sh7750_mmct_write,
sh7750_mmct_readl .endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const sh7750_mmct_write[] = {
invalid_write,
invalid_write,
sh7750_mmct_writel
}; };
SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem) SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
{ {
SH7750State *s; SH7750State *s;
int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
s = g_malloc0(sizeof(SH7750State)); s = g_malloc0(sizeof(SH7750State));
s->cpu = cpu; s->cpu = cpu;
@ -749,11 +752,9 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
&s->iomem, 0x1fc00000, 0x1000); &s->iomem, 0x1fc00000, 0x1000);
memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc); memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc);
sh7750_mm_cache_and_tlb = cpu_register_io_memory(sh7750_mmct_read, memory_region_init_io(&s->mmct_iomem, &sh7750_mmct_ops, s,
sh7750_mmct_write, s, "cache-and-tlb", 0x08000000);
DEVICE_NATIVE_ENDIAN); memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
cpu_register_physical_memory(0xf0000000, 0x08000000,
sh7750_mm_cache_and_tlb);
sh_intc_init(&s->intc, NR_SOURCES, sh_intc_init(&s->intc, NR_SOURCES,
_INTC_ARRAY(mask_registers), _INTC_ARRAY(mask_registers),