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hw/riscv: Add fw_cfg support to virt

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Provides fw_cfg for the virt machine on riscv.  This enables
using e.g.  ramfb later.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Asherah Connor 2021-03-19 10:50:40 +11:00 committed by Alistair Francis
parent db9ab38b81
commit 0489348d0d
3 changed files with 33 additions and 0 deletions
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1
hw/riscv/Kconfig
View File

@ -33,6 +33,7 @@ config RISCV_VIRT
select SIFIVE_PLIC select SIFIVE_PLIC
select SIFIVE_TEST select SIFIVE_TEST
select VIRTIO_MMIO select VIRTIO_MMIO
select FW_CFG_DMA
config SIFIVE_E config SIFIVE_E
bool bool

30
hw/riscv/virt.c
View File

@ -53,6 +53,7 @@ static const MemMapEntry virt_memmap[] = {
[VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
[VIRT_UART0] = { 0x10000000, 0x100 }, [VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 }, [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
[VIRT_FW_CFG] = { 0x10100000, 0x18 },
[VIRT_FLASH] = { 0x20000000, 0x4000000 }, [VIRT_FLASH] = { 0x20000000, 0x4000000 },
[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
@ -507,6 +508,28 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
return dev; return dev;
} }
static FWCfgState *create_fw_cfg(const MachineState *mc)
{
hwaddr base = virt_memmap[VIRT_FW_CFG].base;
hwaddr size = virt_memmap[VIRT_FW_CFG].size;
FWCfgState *fw_cfg;
char *nodename;
fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
&address_space_memory);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
qemu_fdt_add_subnode(mc->fdt, nodename);
qemu_fdt_setprop_string(mc->fdt, nodename,
"compatible", "qemu,fw-cfg-mmio");
qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
2, base, 2, size);
qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
g_free(nodename);
return fw_cfg;
}
static void virt_machine_init(MachineState *machine) static void virt_machine_init(MachineState *machine)
{ {
const MemMapEntry *memmap = virt_memmap; const MemMapEntry *memmap = virt_memmap;
@ -688,6 +711,13 @@ static void virt_machine_init(MachineState *machine)
start_addr = virt_memmap[VIRT_FLASH].base; start_addr = virt_memmap[VIRT_FLASH].base;
} }
/*
* Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
* tree cannot be altered and we get FDT_ERR_NOSPACE.
*/
s->fw_cfg = create_fw_cfg(machine);
rom_set_fw(s->fw_cfg);
/* Compute the fdt load address in dram */ /* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
machine->ram_size, machine->fdt); machine->ram_size, machine->fdt);

2
include/hw/riscv/virt.h
View File

@ -40,6 +40,7 @@ struct RISCVVirtState {
RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
DeviceState *plic[VIRT_SOCKETS_MAX]; DeviceState *plic[VIRT_SOCKETS_MAX];
PFlashCFI01 *flash[2]; PFlashCFI01 *flash[2];
FWCfgState *fw_cfg;
int fdt_size; int fdt_size;
}; };
@ -53,6 +54,7 @@ enum {
VIRT_PLIC, VIRT_PLIC,
VIRT_UART0, VIRT_UART0,
VIRT_VIRTIO, VIRT_VIRTIO,
VIRT_FW_CFG,
VIRT_FLASH, VIRT_FLASH,
VIRT_DRAM, VIRT_DRAM,
VIRT_PCIE_MMIO, VIRT_PCIE_MMIO,