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6d6714bf0c
The clk_tx_i clock must be supplied to the MAC for successful
initialization. On TH1520 SoC, the clock is provided by an internal
divider configured through GMAC_PLLCLK_DIV register when using RGMII
interface. However, currently we don't setup the divider before
initialization of the MAC, resulting in DMA reset failures if the
bootloader/firmware doesn't enable the divider,
[ 7.839601] thead-dwmac ffe7060000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
[ 7.938338] thead-dwmac ffe7060000.ethernet eth0: PHY [stmmac-0:02] driver [RTL8211F Gigabit Ethernet] (irq=POLL)
[ 8.160746] thead-dwmac ffe7060000.ethernet eth0: Failed to reset the dma
[ 8.170118] thead-dwmac ffe7060000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[ 8.179384] thead-dwmac ffe7060000.ethernet eth0: __stmmac_open: Hw setup failed
Let's simply write GMAC_PLLCLK_DIV_EN to GMAC_PLLCLK_DIV to enable the
divider before MAC initialization. Note that for reconfiguring the
divisor, the divider must be disabled first and re-enabled later to make
sure the new divisor take effect.
The exact clock rate doesn't affect MAC's initialization according to my
test. It's set to the speed required by RGMII when the linkspeed is
1Gbps and could be reclocked later after link is up if necessary.
Fixes: 33a1a01e3a ("net: stmmac: Add glue layer for T-HEAD TH1520 SoC")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Link: https://patch.msgid.link/20250815104803.55294-1-ziyao@disroot.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
287 lines
7.5 KiB
C
287 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* T-HEAD DWMAC platform driver
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*
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* Copyright (C) 2021 Alibaba Group Holding Limited.
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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*
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*/
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#include <linux/bitfield.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_net.h>
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#include <linux/platform_device.h>
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#include "stmmac_platform.h"
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#define GMAC_CLK_EN 0x00
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#define GMAC_TX_CLK_EN BIT(1)
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#define GMAC_TX_CLK_N_EN BIT(2)
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#define GMAC_TX_CLK_OUT_EN BIT(3)
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#define GMAC_RX_CLK_EN BIT(4)
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#define GMAC_RX_CLK_N_EN BIT(5)
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#define GMAC_EPHY_REF_CLK_EN BIT(6)
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#define GMAC_RXCLK_DELAY_CTRL 0x04
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#define GMAC_RXCLK_BYPASS BIT(15)
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#define GMAC_RXCLK_INVERT BIT(14)
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#define GMAC_RXCLK_DELAY GENMASK(4, 0)
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#define GMAC_TXCLK_DELAY_CTRL 0x08
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#define GMAC_TXCLK_BYPASS BIT(15)
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#define GMAC_TXCLK_INVERT BIT(14)
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#define GMAC_TXCLK_DELAY GENMASK(4, 0)
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#define GMAC_PLLCLK_DIV 0x0c
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#define GMAC_PLLCLK_DIV_EN BIT(31)
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#define GMAC_PLLCLK_DIV_NUM GENMASK(7, 0)
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#define GMAC_GTXCLK_SEL 0x18
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#define GMAC_GTXCLK_SEL_PLL BIT(0)
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#define GMAC_INTF_CTRL 0x1c
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#define PHY_INTF_MASK BIT(0)
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#define PHY_INTF_RGMII FIELD_PREP(PHY_INTF_MASK, 1)
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#define PHY_INTF_MII_GMII FIELD_PREP(PHY_INTF_MASK, 0)
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#define GMAC_TXCLK_OEN 0x20
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#define TXCLK_DIR_MASK BIT(0)
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#define TXCLK_DIR_OUTPUT FIELD_PREP(TXCLK_DIR_MASK, 0)
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#define TXCLK_DIR_INPUT FIELD_PREP(TXCLK_DIR_MASK, 1)
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struct thead_dwmac {
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struct plat_stmmacenet_data *plat;
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void __iomem *apb_base;
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struct device *dev;
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};
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static int thead_dwmac_set_phy_if(struct plat_stmmacenet_data *plat)
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{
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struct thead_dwmac *dwmac = plat->bsp_priv;
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u32 phyif;
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switch (plat->mac_interface) {
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case PHY_INTERFACE_MODE_MII:
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phyif = PHY_INTF_MII_GMII;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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phyif = PHY_INTF_RGMII;
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break;
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default:
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dev_err(dwmac->dev, "unsupported phy interface %d\n",
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plat->mac_interface);
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return -EINVAL;
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}
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writel(phyif, dwmac->apb_base + GMAC_INTF_CTRL);
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return 0;
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}
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static int thead_dwmac_set_txclk_dir(struct plat_stmmacenet_data *plat)
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{
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struct thead_dwmac *dwmac = plat->bsp_priv;
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u32 txclk_dir;
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switch (plat->mac_interface) {
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case PHY_INTERFACE_MODE_MII:
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txclk_dir = TXCLK_DIR_INPUT;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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txclk_dir = TXCLK_DIR_OUTPUT;
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break;
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default:
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dev_err(dwmac->dev, "unsupported phy interface %d\n",
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plat->mac_interface);
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return -EINVAL;
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}
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writel(txclk_dir, dwmac->apb_base + GMAC_TXCLK_OEN);
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return 0;
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}
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static int thead_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
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phy_interface_t interface, int speed)
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{
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struct thead_dwmac *dwmac = bsp_priv;
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struct plat_stmmacenet_data *plat;
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unsigned long rate;
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long tx_rate;
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u32 div, reg;
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plat = dwmac->plat;
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switch (plat->mac_interface) {
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/* For MII, rxc/txc is provided by phy */
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case PHY_INTERFACE_MODE_MII:
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return 0;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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rate = clk_get_rate(plat->stmmac_clk);
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writel(0, dwmac->apb_base + GMAC_PLLCLK_DIV);
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tx_rate = rgmii_clock(speed);
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if (tx_rate < 0) {
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dev_err(dwmac->dev, "invalid speed %d\n", speed);
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return tx_rate;
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}
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div = rate / tx_rate;
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if (rate != tx_rate * div) {
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dev_err(dwmac->dev, "invalid gmac rate %lu\n", rate);
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return -EINVAL;
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}
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reg = FIELD_PREP(GMAC_PLLCLK_DIV_EN, 1) |
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FIELD_PREP(GMAC_PLLCLK_DIV_NUM, div);
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writel(reg, dwmac->apb_base + GMAC_PLLCLK_DIV);
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return 0;
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default:
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dev_err(dwmac->dev, "unsupported phy interface %d\n",
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plat->mac_interface);
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return -EINVAL;
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}
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}
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static int thead_dwmac_enable_clk(struct plat_stmmacenet_data *plat)
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{
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struct thead_dwmac *dwmac = plat->bsp_priv;
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u32 reg, div;
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switch (plat->mac_interface) {
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case PHY_INTERFACE_MODE_MII:
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reg = GMAC_RX_CLK_EN | GMAC_TX_CLK_EN;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* use pll */
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div = clk_get_rate(plat->stmmac_clk) / rgmii_clock(SPEED_1000);
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reg = FIELD_PREP(GMAC_PLLCLK_DIV_EN, 1) |
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FIELD_PREP(GMAC_PLLCLK_DIV_NUM, div);
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writel(0, dwmac->apb_base + GMAC_PLLCLK_DIV);
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writel(reg, dwmac->apb_base + GMAC_PLLCLK_DIV);
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writel(GMAC_GTXCLK_SEL_PLL, dwmac->apb_base + GMAC_GTXCLK_SEL);
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reg = GMAC_TX_CLK_EN | GMAC_TX_CLK_N_EN | GMAC_TX_CLK_OUT_EN |
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GMAC_RX_CLK_EN | GMAC_RX_CLK_N_EN;
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break;
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default:
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dev_err(dwmac->dev, "unsupported phy interface %d\n",
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plat->mac_interface);
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return -EINVAL;
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}
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writel(reg, dwmac->apb_base + GMAC_CLK_EN);
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return 0;
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}
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static int thead_dwmac_init(struct platform_device *pdev, void *priv)
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{
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struct thead_dwmac *dwmac = priv;
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unsigned int reg;
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int ret;
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ret = thead_dwmac_set_phy_if(dwmac->plat);
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if (ret)
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return ret;
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ret = thead_dwmac_set_txclk_dir(dwmac->plat);
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if (ret)
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return ret;
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reg = readl(dwmac->apb_base + GMAC_RXCLK_DELAY_CTRL);
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reg &= ~(GMAC_RXCLK_DELAY);
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reg |= FIELD_PREP(GMAC_RXCLK_DELAY, 0);
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writel(reg, dwmac->apb_base + GMAC_RXCLK_DELAY_CTRL);
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reg = readl(dwmac->apb_base + GMAC_TXCLK_DELAY_CTRL);
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reg &= ~(GMAC_TXCLK_DELAY);
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reg |= FIELD_PREP(GMAC_TXCLK_DELAY, 0);
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writel(reg, dwmac->apb_base + GMAC_TXCLK_DELAY_CTRL);
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return thead_dwmac_enable_clk(dwmac->plat);
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}
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static int thead_dwmac_probe(struct platform_device *pdev)
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{
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struct stmmac_resources stmmac_res;
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struct plat_stmmacenet_data *plat;
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struct thead_dwmac *dwmac;
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struct clk *apb_clk;
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void __iomem *apb;
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int ret;
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ret = stmmac_get_platform_resources(pdev, &stmmac_res);
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if (ret)
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return dev_err_probe(&pdev->dev, ret,
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"failed to get resources\n");
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plat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
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if (IS_ERR(plat))
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return dev_err_probe(&pdev->dev, PTR_ERR(plat),
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"dt configuration failed\n");
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/*
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* The APB clock is essential for accessing glue registers. However,
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* old devicetrees don't describe it correctly. We continue to probe
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* and emit a warning if it isn't present.
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*/
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apb_clk = devm_clk_get_enabled(&pdev->dev, "apb");
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if (PTR_ERR(apb_clk) == -ENOENT)
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dev_warn(&pdev->dev,
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"cannot get apb clock, link may break after speed changes\n");
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else if (IS_ERR(apb_clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(apb_clk),
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"failed to get apb clock\n");
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dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
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if (!dwmac)
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return -ENOMEM;
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apb = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(apb))
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return dev_err_probe(&pdev->dev, PTR_ERR(apb),
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"failed to remap gmac apb registers\n");
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dwmac->dev = &pdev->dev;
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dwmac->plat = plat;
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dwmac->apb_base = apb;
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plat->bsp_priv = dwmac;
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plat->set_clk_tx_rate = thead_set_clk_tx_rate;
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plat->init = thead_dwmac_init;
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return devm_stmmac_pltfr_probe(pdev, plat, &stmmac_res);
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}
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static const struct of_device_id thead_dwmac_match[] = {
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{ .compatible = "thead,th1520-gmac" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, thead_dwmac_match);
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static struct platform_driver thead_dwmac_driver = {
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.probe = thead_dwmac_probe,
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.driver = {
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.name = "thead-dwmac",
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.pm = &stmmac_pltfr_pm_ops,
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.of_match_table = thead_dwmac_match,
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},
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};
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module_platform_driver(thead_dwmac_driver);
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MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
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MODULE_AUTHOR("Drew Fustini <drew@pdp7.com>");
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MODULE_DESCRIPTION("T-HEAD DWMAC platform driver");
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MODULE_LICENSE("GPL");
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