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17fcb3dc12
This is [1/3] part of hinic3 Ethernet driver initial submission. With this patch hinic3 is a valid kernel module but non-functional driver. The driver parts contained in this patch: Module initialization. PCI driver registration but with empty id_table. Auxiliary driver registration. Net device_ops registration but open/stop are empty stubs. tx/rx logic. All major data structures of the driver are fully introduced with the code that uses them but without their initialization code that requires management interface with the hw. Co-developed-by: Xin Guo <guoxin09@huawei.com> Signed-off-by: Xin Guo <guoxin09@huawei.com> Signed-off-by: Fan Gong <gongfan1@huawei.com> Co-developed-by: Gur Stavi <gur.stavi@huawei.com> Signed-off-by: Gur Stavi <gur.stavi@huawei.com> Link: https://patch.msgid.link/76a137ffdfe115c737c2c224f0c93b60ba53cc16.1747736586.git.gur.stavi@huawei.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
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#ifndef _HINIC3_RX_H_
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#define _HINIC3_RX_H_
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#include <linux/bitfield.h>
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#include <linux/netdevice.h>
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#define RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_MASK GENMASK(4, 0)
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#define RQ_CQE_OFFOLAD_TYPE_IP_TYPE_MASK GENMASK(6, 5)
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#define RQ_CQE_OFFOLAD_TYPE_TUNNEL_PKT_FORMAT_MASK GENMASK(11, 8)
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#define RQ_CQE_OFFOLAD_TYPE_VLAN_EN_MASK BIT(21)
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#define RQ_CQE_OFFOLAD_TYPE_GET(val, member) \
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FIELD_GET(RQ_CQE_OFFOLAD_TYPE_##member##_MASK, val)
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#define RQ_CQE_SGE_VLAN_MASK GENMASK(15, 0)
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#define RQ_CQE_SGE_LEN_MASK GENMASK(31, 16)
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#define RQ_CQE_SGE_GET(val, member) \
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FIELD_GET(RQ_CQE_SGE_##member##_MASK, val)
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#define RQ_CQE_STATUS_CSUM_ERR_MASK GENMASK(15, 0)
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#define RQ_CQE_STATUS_NUM_LRO_MASK GENMASK(23, 16)
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#define RQ_CQE_STATUS_RXDONE_MASK BIT(31)
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#define RQ_CQE_STATUS_GET(val, member) \
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FIELD_GET(RQ_CQE_STATUS_##member##_MASK, val)
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/* RX Completion information that is provided by HW for a specific RX WQE */
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struct hinic3_rq_cqe {
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u32 status;
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u32 vlan_len;
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u32 offload_type;
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u32 rsvd3;
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u32 rsvd4;
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u32 rsvd5;
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u32 rsvd6;
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u32 pkt_info;
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};
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struct hinic3_rq_wqe {
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u32 buf_hi_addr;
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u32 buf_lo_addr;
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u32 cqe_hi_addr;
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u32 cqe_lo_addr;
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};
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struct hinic3_rx_info {
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struct page *page;
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u32 page_offset;
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};
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struct hinic3_rxq {
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struct net_device *netdev;
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u16 q_id;
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u32 q_depth;
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u32 q_mask;
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u16 buf_len;
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u32 buf_len_shift;
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u32 cons_idx;
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u32 delta;
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u32 irq_id;
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u16 msix_entry_idx;
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/* cqe_arr and rx_info are arrays of rq_depth elements. Each element is
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* statically associated (by index) to a specific rq_wqe.
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*/
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struct hinic3_rq_cqe *cqe_arr;
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struct hinic3_rx_info *rx_info;
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struct page_pool *page_pool;
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struct hinic3_io_queue *rq;
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struct hinic3_irq_cfg *irq_cfg;
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u16 next_to_alloc;
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u16 next_to_update;
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struct device *dev; /* device for DMA mapping */
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dma_addr_t cqe_start_paddr;
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} ____cacheline_aligned;
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int hinic3_alloc_rxqs(struct net_device *netdev);
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void hinic3_free_rxqs(struct net_device *netdev);
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int hinic3_rx_poll(struct hinic3_rxq *rxq, int budget);
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#endif
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