mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2025-08-26 06:39:13 +00:00
fbd47be098
Adds complete support for hardware-based PTP (IEEE 1588) timestamping to the AMD XGBE driver. - Initialize and configure the MAC PTP registers based on link speed and reference clock. - Support both 50MHz and 125MHz PTP reference clocks. - Update the driver interface and version data to support PTP clock frequency selection. Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250718185628.4038779-3-Raju.Rangoju@amd.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
477 lines
13 KiB
C
477 lines
13 KiB
C
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
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* Copyright (c) 2014, Synopsys, Inc.
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* All rights reserved
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*/
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/pci.h>
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#include <linux/log2.h>
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#include "xgbe-smn.h"
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#include "xgbe.h"
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#include "xgbe-common.h"
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static int xgbe_config_multi_msi(struct xgbe_prv_data *pdata)
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{
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unsigned int vector_count;
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unsigned int i, j;
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int ret;
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vector_count = XGBE_MSI_BASE_COUNT;
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vector_count += max(pdata->rx_ring_count,
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pdata->tx_ring_count);
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ret = pci_alloc_irq_vectors(pdata->pcidev, XGBE_MSI_MIN_COUNT,
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vector_count, PCI_IRQ_MSI | PCI_IRQ_MSIX);
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if (ret < 0) {
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dev_info(pdata->dev, "multi MSI/MSI-X enablement failed\n");
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return ret;
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}
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pdata->isr_as_bh_work = 1;
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pdata->irq_count = ret;
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pdata->dev_irq = pci_irq_vector(pdata->pcidev, 0);
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pdata->ecc_irq = pci_irq_vector(pdata->pcidev, 1);
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pdata->i2c_irq = pci_irq_vector(pdata->pcidev, 2);
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pdata->an_irq = pci_irq_vector(pdata->pcidev, 3);
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for (i = XGBE_MSI_BASE_COUNT, j = 0; i < ret; i++, j++)
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pdata->channel_irq[j] = pci_irq_vector(pdata->pcidev, i);
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pdata->channel_irq_count = j;
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pdata->per_channel_irq = 1;
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pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
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if (netif_msg_probe(pdata))
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dev_dbg(pdata->dev, "multi %s interrupts enabled\n",
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pdata->pcidev->msix_enabled ? "MSI-X" : "MSI");
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return 0;
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}
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static int xgbe_config_irqs(struct xgbe_prv_data *pdata)
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{
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int ret;
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ret = xgbe_config_multi_msi(pdata);
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if (!ret)
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goto out;
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ret = pci_alloc_irq_vectors(pdata->pcidev, 1, 1,
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PCI_IRQ_INTX | PCI_IRQ_MSI);
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if (ret < 0) {
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dev_info(pdata->dev, "single IRQ enablement failed\n");
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return ret;
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}
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pdata->isr_as_bh_work = pdata->pcidev->msi_enabled ? 1 : 0;
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pdata->irq_count = 1;
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pdata->channel_irq_count = 1;
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pdata->dev_irq = pci_irq_vector(pdata->pcidev, 0);
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pdata->ecc_irq = pci_irq_vector(pdata->pcidev, 0);
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pdata->i2c_irq = pci_irq_vector(pdata->pcidev, 0);
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pdata->an_irq = pci_irq_vector(pdata->pcidev, 0);
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if (netif_msg_probe(pdata))
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dev_dbg(pdata->dev, "single %s interrupt enabled\n",
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pdata->pcidev->msi_enabled ? "MSI" : "legacy");
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out:
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if (netif_msg_probe(pdata)) {
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unsigned int i;
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dev_dbg(pdata->dev, " dev irq=%d\n", pdata->dev_irq);
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dev_dbg(pdata->dev, " ecc irq=%d\n", pdata->ecc_irq);
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dev_dbg(pdata->dev, " i2c irq=%d\n", pdata->i2c_irq);
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dev_dbg(pdata->dev, " an irq=%d\n", pdata->an_irq);
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for (i = 0; i < pdata->channel_irq_count; i++)
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dev_dbg(pdata->dev, " dma%u irq=%d\n",
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i, pdata->channel_irq[i]);
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}
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return 0;
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}
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static int xgbe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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void __iomem * const *iomap_table;
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unsigned int port_addr_size, reg;
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struct device *dev = &pdev->dev;
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struct xgbe_prv_data *pdata;
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unsigned int ma_lo, ma_hi;
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struct pci_dev *rdev;
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int bar_mask, ret;
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u32 address;
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pdata = xgbe_alloc_pdata(dev);
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if (IS_ERR(pdata)) {
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ret = PTR_ERR(pdata);
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goto err_alloc;
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}
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pdata->pcidev = pdev;
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pci_set_drvdata(pdev, pdata);
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/* Get the version data */
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pdata->vdata = (struct xgbe_version_data *)id->driver_data;
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ret = pcim_enable_device(pdev);
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if (ret) {
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dev_err(dev, "pcim_enable_device failed\n");
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goto err_pci_enable;
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}
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/* Obtain the mmio areas for the device */
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bar_mask = pci_select_bars(pdev, IORESOURCE_MEM);
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ret = pcim_iomap_regions(pdev, bar_mask, XGBE_DRV_NAME);
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if (ret) {
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dev_err(dev, "pcim_iomap_regions failed\n");
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goto err_pci_enable;
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}
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iomap_table = pcim_iomap_table(pdev);
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if (!iomap_table) {
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dev_err(dev, "pcim_iomap_table failed\n");
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ret = -ENOMEM;
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goto err_pci_enable;
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}
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pdata->xgmac_regs = iomap_table[XGBE_XGMAC_BAR];
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if (!pdata->xgmac_regs) {
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dev_err(dev, "xgmac ioremap failed\n");
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ret = -ENOMEM;
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goto err_pci_enable;
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}
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pdata->xprop_regs = pdata->xgmac_regs + XGBE_MAC_PROP_OFFSET;
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pdata->xi2c_regs = pdata->xgmac_regs + XGBE_I2C_CTRL_OFFSET;
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if (netif_msg_probe(pdata)) {
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dev_dbg(dev, "xgmac_regs = %p\n", pdata->xgmac_regs);
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dev_dbg(dev, "xprop_regs = %p\n", pdata->xprop_regs);
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dev_dbg(dev, "xi2c_regs = %p\n", pdata->xi2c_regs);
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}
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pdata->xpcs_regs = iomap_table[XGBE_XPCS_BAR];
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if (!pdata->xpcs_regs) {
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dev_err(dev, "xpcs ioremap failed\n");
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ret = -ENOMEM;
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goto err_pci_enable;
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}
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if (netif_msg_probe(pdata))
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dev_dbg(dev, "xpcs_regs = %p\n", pdata->xpcs_regs);
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/* Set the PCS indirect addressing definition registers */
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rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
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if (rdev && rdev->vendor == PCI_VENDOR_ID_AMD) {
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switch (rdev->device) {
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case XGBE_RV_PCI_DEVICE_ID:
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pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
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pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
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break;
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case XGBE_YC_PCI_DEVICE_ID:
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pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF;
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pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT;
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/* Yellow Carp devices do not need cdr workaround */
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pdata->vdata->an_cdr_workaround = 0;
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/* Yellow Carp devices do not need rrc */
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pdata->vdata->enable_rrc = 0;
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break;
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case XGBE_RN_PCI_DEVICE_ID:
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pdata->xpcs_window_def_reg = PCS_V3_RN_WINDOW_DEF;
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pdata->xpcs_window_sel_reg = PCS_V3_RN_WINDOW_SELECT;
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break;
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default:
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pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
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pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
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break;
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}
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} else {
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pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
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pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
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}
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pci_dev_put(rdev);
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/* Configure the PCS indirect addressing support */
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if (pdata->vdata->xpcs_access == XGBE_XPCS_ACCESS_V3) {
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reg = XP_IOREAD(pdata, XP_PROP_0);
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port_addr_size = PCS_RN_PORT_ADDR_SIZE *
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XP_GET_BITS(reg, XP_PROP_0, PORT_ID);
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pdata->smn_base = PCS_RN_SMN_BASE_ADDR + port_addr_size;
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address = pdata->smn_base + (pdata->xpcs_window_def_reg);
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ret = amd_smn_read(0, address, ®);
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if (ret) {
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pci_err(pdata->pcidev, "Failed to read data\n");
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goto err_pci_enable;
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}
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} else {
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reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
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}
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pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
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pdata->xpcs_window <<= 6;
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pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
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pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
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pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
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if (netif_msg_probe(pdata)) {
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dev_dbg(dev, "xpcs window def = %#010x\n",
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pdata->xpcs_window_def_reg);
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dev_dbg(dev, "xpcs window sel = %#010x\n",
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pdata->xpcs_window_sel_reg);
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dev_dbg(dev, "xpcs window = %#010x\n",
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pdata->xpcs_window);
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dev_dbg(dev, "xpcs window size = %#010x\n",
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pdata->xpcs_window_size);
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dev_dbg(dev, "xpcs window mask = %#010x\n",
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pdata->xpcs_window_mask);
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}
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pci_set_master(pdev);
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/* Enable all interrupts in the hardware */
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XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
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/* Retrieve the MAC address */
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ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
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ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
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pdata->mac_addr[0] = ma_lo & 0xff;
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pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
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pdata->mac_addr[2] = (ma_lo >> 16) & 0xff;
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pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
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pdata->mac_addr[4] = ma_hi & 0xff;
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pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
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if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID) ||
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!is_valid_ether_addr(pdata->mac_addr)) {
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dev_err(dev, "invalid mac address\n");
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ret = -EINVAL;
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goto err_pci_enable;
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}
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/* Clock settings */
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pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
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pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
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/* Set the DMA coherency values */
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pdata->coherent = 1;
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pdata->arcr = XGBE_DMA_PCI_ARCR;
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pdata->awcr = XGBE_DMA_PCI_AWCR;
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pdata->awarcr = XGBE_DMA_PCI_AWARCR;
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/* Read the port property registers */
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pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
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pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
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pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
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pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
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pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
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if (netif_msg_probe(pdata)) {
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dev_dbg(dev, "port property 0 = %#010x\n", pdata->pp0);
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dev_dbg(dev, "port property 1 = %#010x\n", pdata->pp1);
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dev_dbg(dev, "port property 2 = %#010x\n", pdata->pp2);
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dev_dbg(dev, "port property 3 = %#010x\n", pdata->pp3);
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dev_dbg(dev, "port property 4 = %#010x\n", pdata->pp4);
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}
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/* Set the maximum channels and queues */
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pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
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MAX_TX_DMA);
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pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
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MAX_RX_DMA);
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pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
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MAX_TX_QUEUES);
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pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
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MAX_RX_QUEUES);
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if (netif_msg_probe(pdata)) {
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dev_dbg(dev, "max tx/rx channel count = %u/%u\n",
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pdata->tx_max_channel_count,
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pdata->rx_max_channel_count);
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dev_dbg(dev, "max tx/rx hw queue count = %u/%u\n",
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pdata->tx_max_q_count, pdata->rx_max_q_count);
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}
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/* Set the hardware channel and queue counts */
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xgbe_set_counts(pdata);
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/* Set the maximum fifo amounts */
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pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
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TX_FIFO_SIZE);
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pdata->tx_max_fifo_size *= 16384;
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pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
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pdata->vdata->tx_max_fifo_size);
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pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
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RX_FIFO_SIZE);
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pdata->rx_max_fifo_size *= 16384;
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pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
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pdata->vdata->rx_max_fifo_size);
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if (netif_msg_probe(pdata))
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dev_dbg(dev, "max tx/rx max fifo size = %u/%u\n",
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pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
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/* Configure interrupt support */
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ret = xgbe_config_irqs(pdata);
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if (ret)
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goto err_pci_enable;
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/* Configure the netdev resource */
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ret = xgbe_config_netdev(pdata);
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if (ret)
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goto err_irq_vectors;
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netdev_notice(pdata->netdev, "net device enabled\n");
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return 0;
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err_irq_vectors:
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pci_free_irq_vectors(pdata->pcidev);
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err_pci_enable:
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xgbe_free_pdata(pdata);
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err_alloc:
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dev_notice(dev, "net device not enabled\n");
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return ret;
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}
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static void xgbe_pci_remove(struct pci_dev *pdev)
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{
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struct xgbe_prv_data *pdata = pci_get_drvdata(pdev);
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xgbe_deconfig_netdev(pdata);
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pci_free_irq_vectors(pdata->pcidev);
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/* Disable all interrupts in the hardware */
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XP_IOWRITE(pdata, XP_INT_EN, 0x0);
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xgbe_free_pdata(pdata);
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}
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static int __maybe_unused xgbe_pci_suspend(struct device *dev)
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{
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struct xgbe_prv_data *pdata = dev_get_drvdata(dev);
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struct net_device *netdev = pdata->netdev;
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int ret = 0;
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if (netif_running(netdev))
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ret = xgbe_powerdown(netdev, XGMAC_DRIVER_CONTEXT);
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pdata->lpm_ctrl = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
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pdata->lpm_ctrl |= MDIO_CTRL1_LPOWER;
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XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
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return ret;
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}
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static int __maybe_unused xgbe_pci_resume(struct device *dev)
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{
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struct xgbe_prv_data *pdata = dev_get_drvdata(dev);
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struct net_device *netdev = pdata->netdev;
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int ret = 0;
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XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
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pdata->lpm_ctrl &= ~MDIO_CTRL1_LPOWER;
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XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl);
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if (netif_running(netdev)) {
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ret = xgbe_powerup(netdev, XGMAC_DRIVER_CONTEXT);
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/* Schedule a restart in case the link or phy state changed
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* while we were powered down.
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*/
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schedule_work(&pdata->restart_work);
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}
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return ret;
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}
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static struct xgbe_version_data xgbe_v3 = {
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.init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
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.xpcs_access = XGBE_XPCS_ACCESS_V3,
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.mmc_64bit = 1,
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.tx_max_fifo_size = 65536,
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.rx_max_fifo_size = 65536,
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.tx_tstamp_workaround = 1,
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.ecc_support = 1,
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.i2c_support = 1,
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.irq_reissue_support = 1,
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.tx_desc_prefetch = 5,
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.rx_desc_prefetch = 5,
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.an_cdr_workaround = 0,
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.enable_rrc = 0,
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};
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static struct xgbe_version_data xgbe_v2a = {
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.init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
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.xpcs_access = XGBE_XPCS_ACCESS_V2,
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.mmc_64bit = 1,
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.tx_max_fifo_size = 229376,
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|
.rx_max_fifo_size = 229376,
|
|
.tx_tstamp_workaround = 1,
|
|
.tstamp_ptp_clock_freq = 1,
|
|
.ecc_support = 1,
|
|
.i2c_support = 1,
|
|
.irq_reissue_support = 1,
|
|
.tx_desc_prefetch = 5,
|
|
.rx_desc_prefetch = 5,
|
|
.an_cdr_workaround = 1,
|
|
.enable_rrc = 1,
|
|
};
|
|
|
|
static struct xgbe_version_data xgbe_v2b = {
|
|
.init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
|
|
.xpcs_access = XGBE_XPCS_ACCESS_V2,
|
|
.mmc_64bit = 1,
|
|
.tx_max_fifo_size = 65536,
|
|
.rx_max_fifo_size = 65536,
|
|
.tx_tstamp_workaround = 1,
|
|
.tstamp_ptp_clock_freq = 1,
|
|
.ecc_support = 1,
|
|
.i2c_support = 1,
|
|
.irq_reissue_support = 1,
|
|
.tx_desc_prefetch = 5,
|
|
.rx_desc_prefetch = 5,
|
|
.an_cdr_workaround = 1,
|
|
.enable_rrc = 1,
|
|
};
|
|
|
|
static const struct pci_device_id xgbe_pci_table[] = {
|
|
{ PCI_VDEVICE(AMD, 0x1458),
|
|
.driver_data = (kernel_ulong_t)&xgbe_v2a },
|
|
{ PCI_VDEVICE(AMD, 0x1459),
|
|
.driver_data = (kernel_ulong_t)&xgbe_v2b },
|
|
{ PCI_VDEVICE(AMD, 0x1641),
|
|
.driver_data = (kernel_ulong_t)&xgbe_v3 },
|
|
/* Last entry must be zero */
|
|
{ 0, }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, xgbe_pci_table);
|
|
|
|
static SIMPLE_DEV_PM_OPS(xgbe_pci_pm_ops, xgbe_pci_suspend, xgbe_pci_resume);
|
|
|
|
static struct pci_driver xgbe_driver = {
|
|
.name = XGBE_DRV_NAME,
|
|
.id_table = xgbe_pci_table,
|
|
.probe = xgbe_pci_probe,
|
|
.remove = xgbe_pci_remove,
|
|
.driver = {
|
|
.pm = &xgbe_pci_pm_ops,
|
|
}
|
|
};
|
|
|
|
int xgbe_pci_init(void)
|
|
{
|
|
return pci_register_driver(&xgbe_driver);
|
|
}
|
|
|
|
void xgbe_pci_exit(void)
|
|
{
|
|
pci_unregister_driver(&xgbe_driver);
|
|
}
|