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2401dc4dcd
Add support to enable Memory Controller (MC) and External Memory Controller (EMC) drivers for Tegra264. The nodes for MC and EMC are mostly the same as Tegra234 but differ in number of channels and interrupt numbers. The patch also adds the bandwidth manager definitions required for Tegra264 and uses them to populate the memory client table. All of these are needed to properly enable memory interconnect (ICC) support. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250709222147.3758356-3-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
314 lines
8.2 KiB
C
314 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <dt-bindings/memory/nvidia,tegra264.h>
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#include <linux/interconnect.h>
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#include <linux/of_device.h>
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#include <linux/tegra-icc.h>
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#include <soc/tegra/bpmp.h>
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#include <soc/tegra/mc.h>
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#include "mc.h"
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#include "tegra264-bwmgr.h"
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/*
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* MC Client entries are sorted in the increasing order of the
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* override and security register offsets.
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*/
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static const struct tegra_mc_client tegra264_mc_clients[] = {
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{
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.id = TEGRA264_MEMORY_CLIENT_HDAR,
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.name = "hdar",
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.bpmp_id = TEGRA264_BWMGR_HDA,
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.type = TEGRA_ICC_ISO_AUDIO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_HDAW,
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.name = "hdaw",
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.bpmp_id = TEGRA264_BWMGR_HDA,
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.type = TEGRA_ICC_ISO_AUDIO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_MGBE0R,
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.name = "mgbe0r",
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.bpmp_id = TEGRA264_BWMGR_EQOS,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_MGBE0W,
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.name = "mgbe0w",
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.bpmp_id = TEGRA264_BWMGR_EQOS,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_MGBE1R,
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.name = "mgbe1r",
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.bpmp_id = TEGRA264_BWMGR_EQOS,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_MGBE1W,
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.name = "mgbe1w",
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.bpmp_id = TEGRA264_BWMGR_EQOS,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_SDMMC0R,
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.name = "sdmmc0r",
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.bpmp_id = TEGRA264_BWMGR_SDMMC_1,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_SDMMC0W,
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.name = "sdmmc0w",
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.bpmp_id = TEGRA264_BWMGR_SDMMC_1,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_VICR,
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.name = "vicr",
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.bpmp_id = TEGRA264_BWMGR_VIC,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_VICW,
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.name = "vicw",
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.bpmp_id = TEGRA264_BWMGR_VIC,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_APER,
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.name = "aper",
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.bpmp_id = TEGRA264_BWMGR_APE,
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.type = TEGRA_ICC_ISO_AUDIO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_APEW,
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.name = "apew",
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.bpmp_id = TEGRA264_BWMGR_APE,
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.type = TEGRA_ICC_ISO_AUDIO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_APEDMAR,
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.name = "apedmar",
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.bpmp_id = TEGRA264_BWMGR_APEDMA,
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.type = TEGRA_ICC_ISO_AUDIO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_APEDMAW,
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.name = "apedmaw",
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.bpmp_id = TEGRA264_BWMGR_APEDMA,
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.type = TEGRA_ICC_ISO_AUDIO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_VIFALCONR,
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.name = "vifalconr",
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.bpmp_id = TEGRA264_BWMGR_VIFAL,
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.type = TEGRA_ICC_ISO_VIFAL,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_VIFALCONW,
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.name = "vifalconw",
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.bpmp_id = TEGRA264_BWMGR_VIFAL,
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.type = TEGRA_ICC_ISO_VIFAL,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_RCER,
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.name = "rcer",
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.bpmp_id = TEGRA264_BWMGR_RCE,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_RCEW,
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.name = "rcew",
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.bpmp_id = TEGRA264_BWMGR_RCE,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_PCIE0W,
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.name = "pcie0w",
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.bpmp_id = TEGRA264_BWMGR_PCIE_0,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_PCIE1R,
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.name = "pcie1r",
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.bpmp_id = TEGRA264_BWMGR_PCIE_1,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_PCIE1W,
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.name = "pcie1w",
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.bpmp_id = TEGRA264_BWMGR_PCIE_1,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_PCIE2AR,
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.name = "pcie2ar",
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.bpmp_id = TEGRA264_BWMGR_PCIE_2,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_PCIE2AW,
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.name = "pcie2aw",
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.bpmp_id = TEGRA264_BWMGR_PCIE_2,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_PCIE3R,
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.name = "pcie3r",
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.bpmp_id = TEGRA264_BWMGR_PCIE_3,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_PCIE3W,
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.name = "pcie3w",
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.bpmp_id = TEGRA264_BWMGR_PCIE_3,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_PCIE4R,
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.name = "pcie4r",
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.bpmp_id = TEGRA264_BWMGR_PCIE_4,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_PCIE4W,
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.name = "pcie4w",
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.bpmp_id = TEGRA264_BWMGR_PCIE_4,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_PCIE5R,
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.name = "pcie5r",
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.bpmp_id = TEGRA264_BWMGR_PCIE_5,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_PCIE5W,
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.name = "pcie5w",
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.bpmp_id = TEGRA264_BWMGR_PCIE_5,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_GPUR02MC,
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.name = "gpur02mc",
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.bpmp_id = TEGRA264_BWMGR_GPU,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_GPUW02MC,
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.name = "gpuw02mc",
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.bpmp_id = TEGRA264_BWMGR_GPU,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_NVDECSRD2MC,
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.name = "nvdecsrd2mc",
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.bpmp_id = TEGRA264_BWMGR_NVDEC,
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.type = TEGRA_ICC_NISO,
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}, {
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.id = TEGRA264_MEMORY_CLIENT_NVDECSWR2MC,
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.name = "nvdecswr2mc",
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.bpmp_id = TEGRA264_BWMGR_NVDEC,
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.type = TEGRA_ICC_NISO,
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},
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};
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/*
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* tegra264_mc_icc_set() - Pass MC client info to the BPMP-FW
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* @src: ICC node for Memory Controller's (MC) Client
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* @dst: ICC node for Memory Controller (MC)
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*
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* Passing the current request info from the MC to the BPMP-FW where
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* LA and PTSA registers are accessed and the final EMC freq is set
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* based on client_id, type, latency and bandwidth.
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* icc_set_bw() makes set_bw calls for both MC and EMC providers in
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* sequence. Both the calls are protected by 'mutex_lock(&icc_lock)'.
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* So, the data passed won't be updated by concurrent set calls from
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* other clients.
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*/
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static int tegra264_mc_icc_set(struct icc_node *src, struct icc_node *dst)
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{
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struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider);
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struct mrq_bwmgr_int_request bwmgr_req = { 0 };
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struct mrq_bwmgr_int_response bwmgr_resp = { 0 };
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const struct tegra_mc_client *pclient = src->data;
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struct tegra_bpmp_message msg;
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int ret;
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/*
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* Same Src and Dst node will happen during boot from icc_node_add().
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* This can be used to pre-initialize and set bandwidth for all clients
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* before their drivers are loaded. We are skipping this case as for us,
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* the pre-initialization already happened in Bootloader(MB2) and BPMP-FW.
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*/
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if (src->id == dst->id)
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return 0;
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if (!mc->bwmgr_mrq_supported)
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return 0;
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if (!mc->bpmp) {
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dev_err(mc->dev, "BPMP reference NULL\n");
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return -ENOENT;
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}
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if (pclient->type == TEGRA_ICC_NISO)
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bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw;
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else
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bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw;
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bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id;
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bwmgr_req.cmd = CMD_BWMGR_INT_CALC_AND_SET;
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bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw;
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bwmgr_req.bwmgr_calc_set_req.floor_unit = BWMGR_INT_UNIT_KBPS;
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memset(&msg, 0, sizeof(msg));
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msg.mrq = MRQ_BWMGR_INT;
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msg.tx.data = &bwmgr_req;
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msg.tx.size = sizeof(bwmgr_req);
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msg.rx.data = &bwmgr_resp;
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msg.rx.size = sizeof(bwmgr_resp);
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ret = tegra_bpmp_transfer(mc->bpmp, &msg);
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if (ret < 0) {
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dev_err(mc->dev, "BPMP transfer failed: %d\n", ret);
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goto error;
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}
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if (msg.rx.ret < 0) {
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pr_err("failed to set bandwidth for %u: %d\n",
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bwmgr_req.bwmgr_calc_set_req.client_id, msg.rx.ret);
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ret = -EINVAL;
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}
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error:
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return ret;
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}
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static int tegra264_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
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u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
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{
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struct icc_provider *p = node->provider;
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struct tegra_mc *mc = icc_provider_to_tegra_mc(p);
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if (!mc->bwmgr_mrq_supported)
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return 0;
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*agg_avg += avg_bw;
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*agg_peak = max(*agg_peak, peak_bw);
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return 0;
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}
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static int tegra264_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak)
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{
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*avg = 0;
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*peak = 0;
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return 0;
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}
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static const struct tegra_mc_icc_ops tegra264_mc_icc_ops = {
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.xlate = tegra_mc_icc_xlate,
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.aggregate = tegra264_mc_icc_aggregate,
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.get_bw = tegra264_mc_icc_get_init_bw,
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.set = tegra264_mc_icc_set,
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};
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const struct tegra_mc_soc tegra264_mc_soc = {
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.num_clients = ARRAY_SIZE(tegra264_mc_clients),
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.clients = tegra264_mc_clients,
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.num_address_bits = 40,
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.num_channels = 16,
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.client_id_mask = 0x1ff,
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.intmask = MC_INT_DECERR_ROUTE_SANITY |
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MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
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MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
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MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
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.has_addr_hi_reg = true,
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.ops = &tegra186_mc_ops,
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.icc_ops = &tegra264_mc_icc_ops,
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.ch_intmask = 0x0000ff00,
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.global_intstatus_channel_shift = 8,
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/*
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* Additionally, there are lite carveouts but those are not currently
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* supported.
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*/
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.num_carveouts = 32,
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};
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