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This commit supplies shutdown callback for iommu driver. The shutdown callback resets necessary registers so that newly booted kernel can pass riscv_iommu_init_check() after kexec. Also, the shutdown callback resets iommu mode to bare instead of off so that new kernel can still use PCIE devices even when CONFIG_RISCV_IOMMU is not enabled. Signed-off-by: Xu Lu <luxu.kernel@bytedance.com> Link: https://lore.kernel.org/r/20250103093220.38106-3-luxu.kernel@bytedance.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
165 lines
4.5 KiB
C
165 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* RISC-V IOMMU as a platform device
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*
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* Copyright © 2023 FORTH-ICS/CARV
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* Copyright © 2023-2024 Rivos Inc.
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*
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* Authors
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* Nick Kossifidis <mick@ics.forth.gr>
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* Tomasz Jeznach <tjeznach@rivosinc.com>
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*/
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#include <linux/kernel.h>
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#include <linux/msi.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include "iommu-bits.h"
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#include "iommu.h"
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static void riscv_iommu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
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{
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struct device *dev = msi_desc_to_dev(desc);
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struct riscv_iommu_device *iommu = dev_get_drvdata(dev);
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u16 idx = desc->msi_index;
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u64 addr;
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addr = ((u64)msg->address_hi << 32) | msg->address_lo;
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if (addr != (addr & RISCV_IOMMU_MSI_CFG_TBL_ADDR)) {
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dev_err_once(dev,
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"uh oh, the IOMMU can't send MSIs to 0x%llx, sending to 0x%llx instead\n",
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addr, addr & RISCV_IOMMU_MSI_CFG_TBL_ADDR);
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}
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addr &= RISCV_IOMMU_MSI_CFG_TBL_ADDR;
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riscv_iommu_writeq(iommu, RISCV_IOMMU_REG_MSI_CFG_TBL_ADDR(idx), addr);
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riscv_iommu_writel(iommu, RISCV_IOMMU_REG_MSI_CFG_TBL_DATA(idx), msg->data);
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riscv_iommu_writel(iommu, RISCV_IOMMU_REG_MSI_CFG_TBL_CTRL(idx), 0);
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}
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static int riscv_iommu_platform_probe(struct platform_device *pdev)
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{
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enum riscv_iommu_igs_settings igs;
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struct device *dev = &pdev->dev;
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struct riscv_iommu_device *iommu = NULL;
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struct resource *res = NULL;
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int vec, ret;
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iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
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if (!iommu)
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return -ENOMEM;
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iommu->dev = dev;
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iommu->reg = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(iommu->reg))
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return dev_err_probe(dev, PTR_ERR(iommu->reg),
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"could not map register region\n");
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dev_set_drvdata(dev, iommu);
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/* Check device reported capabilities / features. */
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iommu->caps = riscv_iommu_readq(iommu, RISCV_IOMMU_REG_CAPABILITIES);
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iommu->fctl = riscv_iommu_readl(iommu, RISCV_IOMMU_REG_FCTL);
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iommu->irqs_count = platform_irq_count(pdev);
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if (iommu->irqs_count <= 0)
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return dev_err_probe(dev, -ENODEV,
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"no IRQ resources provided\n");
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if (iommu->irqs_count > RISCV_IOMMU_INTR_COUNT)
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iommu->irqs_count = RISCV_IOMMU_INTR_COUNT;
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igs = FIELD_GET(RISCV_IOMMU_CAPABILITIES_IGS, iommu->caps);
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switch (igs) {
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case RISCV_IOMMU_CAPABILITIES_IGS_BOTH:
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case RISCV_IOMMU_CAPABILITIES_IGS_MSI:
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if (is_of_node(dev->fwnode))
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of_msi_configure(dev, to_of_node(dev->fwnode));
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if (!dev_get_msi_domain(dev)) {
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dev_warn(dev, "failed to find an MSI domain\n");
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goto msi_fail;
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}
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ret = platform_device_msi_init_and_alloc_irqs(dev, iommu->irqs_count,
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riscv_iommu_write_msi_msg);
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if (ret) {
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dev_warn(dev, "failed to allocate MSIs\n");
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goto msi_fail;
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}
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for (vec = 0; vec < iommu->irqs_count; vec++)
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iommu->irqs[vec] = msi_get_virq(dev, vec);
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/* Enable message-signaled interrupts, fctl.WSI */
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if (iommu->fctl & RISCV_IOMMU_FCTL_WSI) {
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iommu->fctl ^= RISCV_IOMMU_FCTL_WSI;
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riscv_iommu_writel(iommu, RISCV_IOMMU_REG_FCTL, iommu->fctl);
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}
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dev_info(dev, "using MSIs\n");
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break;
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msi_fail:
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if (igs != RISCV_IOMMU_CAPABILITIES_IGS_BOTH) {
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return dev_err_probe(dev, -ENODEV,
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"unable to use wire-signaled interrupts\n");
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}
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fallthrough;
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case RISCV_IOMMU_CAPABILITIES_IGS_WSI:
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for (vec = 0; vec < iommu->irqs_count; vec++)
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iommu->irqs[vec] = platform_get_irq(pdev, vec);
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/* Enable wire-signaled interrupts, fctl.WSI */
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if (!(iommu->fctl & RISCV_IOMMU_FCTL_WSI)) {
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iommu->fctl |= RISCV_IOMMU_FCTL_WSI;
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riscv_iommu_writel(iommu, RISCV_IOMMU_REG_FCTL, iommu->fctl);
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}
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dev_info(dev, "using wire-signaled interrupts\n");
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break;
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default:
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return dev_err_probe(dev, -ENODEV, "invalid IGS\n");
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}
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return riscv_iommu_init(iommu);
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};
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static void riscv_iommu_platform_remove(struct platform_device *pdev)
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{
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struct riscv_iommu_device *iommu = dev_get_drvdata(&pdev->dev);
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bool msi = !(iommu->fctl & RISCV_IOMMU_FCTL_WSI);
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riscv_iommu_remove(iommu);
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if (msi)
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platform_device_msi_free_irqs_all(&pdev->dev);
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};
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static void riscv_iommu_platform_shutdown(struct platform_device *pdev)
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{
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riscv_iommu_disable(dev_get_drvdata(&pdev->dev));
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};
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static const struct of_device_id riscv_iommu_of_match[] = {
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{.compatible = "riscv,iommu",},
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{},
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};
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static struct platform_driver riscv_iommu_platform_driver = {
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.probe = riscv_iommu_platform_probe,
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.remove = riscv_iommu_platform_remove,
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.shutdown = riscv_iommu_platform_shutdown,
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.driver = {
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.name = "riscv,iommu",
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.of_match_table = riscv_iommu_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(riscv_iommu_platform_driver);
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