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d2de4410a8
The WA requires KMD to disable DOP clock gating during a semaphore
wait and also ensure that idle delay for every CS is lower than the
idle wait time in the PWRCTX_MAXCNT register. Default values for these
registers already comply with this restriction.
v2: Store timestamp_base in gt info and other comments (Daniele)
v3: Skip WA check for VF
v4: Review comments (Matt Roper)
v5: Cleanup the clock functions and use reg_field_get (Matt Roper)
v6: Fix checkpatch issue
v7: Fix CI issue
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250320175123.3026754-1-vinay.belgaumkar@intel.com
(cherry picked from commit 7c53ff050b)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
113 lines
2.8 KiB
C
113 lines
2.8 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include <linux/math64.h>
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#include "xe_gt_clock.h"
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#include "regs/xe_gt_regs.h"
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#include "regs/xe_regs.h"
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#include "xe_assert.h"
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#include "xe_device.h"
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#include "xe_gt.h"
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#include "xe_gt_printk.h"
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#include "xe_macros.h"
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#include "xe_mmio.h"
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#define f19_2_mhz 19200000
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#define f24_mhz 24000000
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#define f25_mhz 25000000
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#define f38_4_mhz 38400000
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#define ts_base_83 83333
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#define ts_base_52 52083
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#define ts_base_80 80000
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static void read_crystal_clock(struct xe_gt *gt, u32 rpm_config_reg, u32 *freq,
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u32 *timestamp_base)
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{
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u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK,
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rpm_config_reg);
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switch (crystal_clock) {
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case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
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*freq = f24_mhz;
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*timestamp_base = ts_base_83;
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return;
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case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
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*freq = f19_2_mhz;
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*timestamp_base = ts_base_52;
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return;
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case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
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*freq = f38_4_mhz;
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*timestamp_base = ts_base_52;
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return;
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case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
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*freq = f25_mhz;
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*timestamp_base = ts_base_80;
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return;
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default:
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xe_gt_warn(gt, "Invalid crystal clock frequency: %u", crystal_clock);
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*freq = 0;
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*timestamp_base = 0;
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return;
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}
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}
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static void check_ctc_mode(struct xe_gt *gt)
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{
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/*
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* CTC_MODE[0] = 1 is definitely not supported for Xe2 and later
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* platforms. In theory it could be a valid setting for pre-Xe2
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* platforms, but there's no documentation on how to properly handle
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* this case. Reading TIMESTAMP_OVERRIDE, as the driver attempted in
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* the past has been confirmed as incorrect by the hardware architects.
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*
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* For now just warn if we ever encounter hardware in the wild that
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* has this setting and move on as if it hadn't been set.
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*/
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if (xe_mmio_read32(>->mmio, CTC_MODE) & CTC_SOURCE_DIVIDE_LOGIC)
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xe_gt_warn(gt, "CTC_MODE[0] is set; this is unexpected and undocumented\n");
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}
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int xe_gt_clock_init(struct xe_gt *gt)
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{
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u32 freq;
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u32 c0;
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if (!IS_SRIOV_VF(gt_to_xe(gt)))
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check_ctc_mode(gt);
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c0 = xe_mmio_read32(>->mmio, RPM_CONFIG0);
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read_crystal_clock(gt, c0, &freq, >->info.timestamp_base);
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/*
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* Now figure out how the command stream's timestamp
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* register increments from this frequency (it might
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* increment only every few clock cycle).
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*/
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freq >>= 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0);
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gt->info.reference_clock = freq;
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return 0;
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}
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static u64 div_u64_roundup(u64 n, u32 d)
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{
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return div_u64(n + d - 1, d);
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}
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/**
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* xe_gt_clock_interval_to_ms - Convert sampled GT clock ticks to msec
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*
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* @gt: the &xe_gt
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* @count: count of GT clock ticks
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*
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* Returns: time in msec
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*/
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u64 xe_gt_clock_interval_to_ms(struct xe_gt *gt, u64 count)
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{
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return div_u64_roundup(count * MSEC_PER_SEC, gt->info.reference_clock);
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}
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