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8d4aec43f6
Update the register definitions in xe_lrc_layout.h to align with the official hardware specification (Bspec) terminology. Specifically: - rename PVC_CTX_ACC_CTR_THOLD to CTX_ACC_CTR_THOLD - rename PVC_CTX_ASID to CTX_ASID Signed-off-by: Xin Wang <x.wang@intel.com> Reviewed-by: Stuart Summers <stuart.summers@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20250711060924.7373-1-x.wang@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
47 lines
1.6 KiB
C
47 lines
1.6 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_LRC_LAYOUT_H_
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#define _XE_LRC_LAYOUT_H_
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#define CTX_CONTEXT_CONTROL (0x02 + 1)
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#define CTX_RING_HEAD (0x04 + 1)
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#define CTX_RING_TAIL (0x06 + 1)
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#define CTX_RING_START (0x08 + 1)
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#define CTX_RING_CTL (0x0a + 1)
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#define CTX_BB_PER_CTX_PTR (0x12 + 1)
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#define CTX_CS_INDIRECT_CTX (0x14 + 1)
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#define CTX_CS_INDIRECT_CTX_OFFSET (0x16 + 1)
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#define CTX_TIMESTAMP (0x22 + 1)
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#define CTX_TIMESTAMP_UDW (0x24 + 1)
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#define CTX_INDIRECT_RING_STATE (0x26 + 1)
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#define CTX_ACC_CTR_THOLD (0x2a + 1)
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#define CTX_ASID (0x2e + 1)
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#define CTX_PDP0_UDW (0x30 + 1)
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#define CTX_PDP0_LDW (0x32 + 1)
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#define CTX_LRM_INT_MASK_ENABLE 0x50
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#define CTX_INT_MASK_ENABLE_REG (CTX_LRM_INT_MASK_ENABLE + 1)
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#define CTX_INT_MASK_ENABLE_PTR (CTX_LRM_INT_MASK_ENABLE + 2)
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#define CTX_LRI_INT_REPORT_PTR 0x55
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#define CTX_INT_STATUS_REPORT_REG (CTX_LRI_INT_REPORT_PTR + 1)
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#define CTX_INT_STATUS_REPORT_PTR (CTX_LRI_INT_REPORT_PTR + 2)
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#define CTX_INT_SRC_REPORT_REG (CTX_LRI_INT_REPORT_PTR + 3)
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#define CTX_INT_SRC_REPORT_PTR (CTX_LRI_INT_REPORT_PTR + 4)
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#define CTX_CS_INT_VEC_REG 0x5a
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#define CTX_CS_INT_VEC_DATA (CTX_CS_INT_VEC_REG + 1)
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#define INDIRECT_CTX_RING_HEAD (0x02 + 1)
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#define INDIRECT_CTX_RING_TAIL (0x04 + 1)
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#define INDIRECT_CTX_RING_START (0x06 + 1)
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#define INDIRECT_CTX_RING_START_UDW (0x08 + 1)
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#define INDIRECT_CTX_RING_CTL (0x0a + 1)
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#define CTX_INDIRECT_CTX_OFFSET_MASK REG_GENMASK(15, 6)
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#define CTX_INDIRECT_CTX_OFFSET_DEFAULT REG_FIELD_PREP(CTX_INDIRECT_CTX_OFFSET_MASK, 0xd)
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#endif
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