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f0e53aadd7
Adding adaption/glue layer where the I2C host adapter (Synopsys DesignWare I2C adapter) and the I2C clients (the microcontroller units) are enumerated. The microcontroller units (MCU) that are attached to the GPU depend on the OEM. The initially supported MCU will be the Add-In Management Controller (AMC). Co-developed-by: Michael J. Ruhl <michael.j.ruhl@intel.com> Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com> Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://lore.kernel.org/r/20250701122252.2590230-4-heikki.krogerus@linux.intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> [Rodrigo fixed the co-developed tags and SPDX format in the .c file]
92 lines
3.7 KiB
C
92 lines
3.7 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#ifndef _XE_IRQ_REGS_H_
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#define _XE_IRQ_REGS_H_
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#include "regs/xe_reg_defs.h"
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#define PCU_IRQ_OFFSET 0x444e0
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#define GU_MISC_IRQ_OFFSET 0x444f0
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#define GU_MISC_GSE REG_BIT(27)
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#define DG1_MSTR_TILE_INTR XE_REG(0x190008)
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#define DG1_MSTR_IRQ REG_BIT(31)
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#define DG1_MSTR_TILE(t) REG_BIT(t)
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#define GFX_MSTR_IRQ XE_REG(0x190010, XE_REG_OPTION_VF)
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#define MASTER_IRQ REG_BIT(31)
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#define GU_MISC_IRQ REG_BIT(29)
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#define DISPLAY_IRQ REG_BIT(16)
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#define I2C_IRQ REG_BIT(12)
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#define GT_DW_IRQ(x) REG_BIT(x)
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/*
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* Note: Interrupt registers 1900xx are VF accessible only until version 12.50.
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* On newer platforms, VFs are using memory-based interrupts instead.
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* However, for simplicity we keep this XE_REG_OPTION_VF tag intact.
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*/
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#define GT_INTR_DW(x) XE_REG(0x190018 + ((x) * 4), XE_REG_OPTION_VF)
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#define INTR_GSC REG_BIT(31)
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#define INTR_GUC REG_BIT(25)
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#define INTR_MGUC REG_BIT(24)
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#define INTR_BCS8 REG_BIT(23)
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#define INTR_BCS(x) REG_BIT(15 - (x))
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#define INTR_CCS(x) REG_BIT(4 + (x))
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#define INTR_RCS0 REG_BIT(0)
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#define INTR_VECS(x) REG_BIT(31 - (x))
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#define INTR_VCS(x) REG_BIT(x)
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#define RENDER_COPY_INTR_ENABLE XE_REG(0x190030, XE_REG_OPTION_VF)
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#define VCS_VECS_INTR_ENABLE XE_REG(0x190034, XE_REG_OPTION_VF)
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#define GUC_SG_INTR_ENABLE XE_REG(0x190038, XE_REG_OPTION_VF)
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#define ENGINE1_MASK REG_GENMASK(31, 16)
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#define ENGINE0_MASK REG_GENMASK(15, 0)
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#define GPM_WGBOXPERF_INTR_ENABLE XE_REG(0x19003c, XE_REG_OPTION_VF)
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#define CRYPTO_RSVD_INTR_ENABLE XE_REG(0x190040)
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#define GUNIT_GSC_INTR_ENABLE XE_REG(0x190044, XE_REG_OPTION_VF)
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#define CCS_RSVD_INTR_ENABLE XE_REG(0x190048, XE_REG_OPTION_VF)
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#define INTR_IDENTITY_REG(x) XE_REG(0x190060 + ((x) * 4), XE_REG_OPTION_VF)
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#define INTR_DATA_VALID REG_BIT(31)
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#define INTR_ENGINE_INSTANCE(x) REG_FIELD_GET(GENMASK(25, 20), x)
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#define INTR_ENGINE_CLASS(x) REG_FIELD_GET(GENMASK(18, 16), x)
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#define INTR_ENGINE_INTR(x) REG_FIELD_GET(GENMASK(15, 0), x)
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#define OTHER_GUC_INSTANCE 0
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#define OTHER_GSC_HECI2_INSTANCE 3
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#define OTHER_KCR_INSTANCE 4
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#define OTHER_GSC_INSTANCE 6
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#define IIR_REG_SELECTOR(x) XE_REG(0x190070 + ((x) * 4), XE_REG_OPTION_VF)
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#define RCS0_RSVD_INTR_MASK XE_REG(0x190090, XE_REG_OPTION_VF)
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#define BCS_RSVD_INTR_MASK XE_REG(0x1900a0, XE_REG_OPTION_VF)
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#define VCS0_VCS1_INTR_MASK XE_REG(0x1900a8, XE_REG_OPTION_VF)
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#define VCS2_VCS3_INTR_MASK XE_REG(0x1900ac, XE_REG_OPTION_VF)
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#define VECS0_VECS1_INTR_MASK XE_REG(0x1900d0, XE_REG_OPTION_VF)
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#define HECI2_RSVD_INTR_MASK XE_REG(0x1900e4)
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#define GUC_SG_INTR_MASK XE_REG(0x1900e8, XE_REG_OPTION_VF)
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#define GPM_WGBOXPERF_INTR_MASK XE_REG(0x1900ec, XE_REG_OPTION_VF)
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#define CRYPTO_RSVD_INTR_MASK XE_REG(0x1900f0)
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#define GUNIT_GSC_INTR_MASK XE_REG(0x1900f4, XE_REG_OPTION_VF)
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#define CCS0_CCS1_INTR_MASK XE_REG(0x190100)
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#define CCS2_CCS3_INTR_MASK XE_REG(0x190104)
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#define XEHPC_BCS1_BCS2_INTR_MASK XE_REG(0x190110)
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#define XEHPC_BCS3_BCS4_INTR_MASK XE_REG(0x190114)
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#define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
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#define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
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#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)
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#define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8)
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#define GSC_ER_COMPLETE REG_BIT(5)
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#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT REG_BIT(4)
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#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
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#define GT_RENDER_USER_INTERRUPT REG_BIT(0)
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/* irqs for OTHER_KCR_INSTANCE */
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#define KCR_PXP_STATE_TERMINATED_INTERRUPT REG_BIT(1)
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#define KCR_APP_TERMINATED_PER_FW_REQ_INTERRUPT REG_BIT(2)
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#define KCR_PXP_STATE_RESET_COMPLETE_INTERRUPT REG_BIT(3)
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#endif
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