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87e1ebbafb
Check NVM access mode from GSC FW status registers and overwrite access status read from SPI descriptor, if needed. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Link: https://lore.kernel.org/r/20250617145159.3803852-8-alexander.usyskin@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
57 lines
1.7 KiB
C
57 lines
1.7 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_GSC_REGS_H_
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#define _XE_GSC_REGS_H_
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include "regs/xe_reg_defs.h"
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/* Definitions of GSC H/W registers, bits, etc */
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#define MTL_GSC_HECI1_BASE 0x00116000
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#define MTL_GSC_HECI2_BASE 0x00117000
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#define DG1_GSC_HECI2_BASE 0x00259000
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#define PVC_GSC_HECI2_BASE 0x00285000
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#define DG2_GSC_HECI2_BASE 0x00374000
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#define HECI_H_CSR(base) XE_REG((base) + 0x4)
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#define HECI_H_CSR_IE REG_BIT(0)
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#define HECI_H_CSR_IS REG_BIT(1)
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#define HECI_H_CSR_IG REG_BIT(2)
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#define HECI_H_CSR_RDY REG_BIT(3)
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#define HECI_H_CSR_RST REG_BIT(4)
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/*
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* The FWSTS register values are FW defined and can be different between
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* HECI1 and HECI2
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*/
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#define HECI_FWSTS1(base) XE_REG((base) + 0xc40)
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#define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)
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#define HECI1_FWSTS1_CURRENT_STATE_RESET 0
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#define HECI1_FWSTS1_PROXY_STATE_NORMAL 5
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#define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9)
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#define HECI_FWSTS2(base) XE_REG((base) + 0xc48)
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#define HECI_FWSTS3(base) XE_REG((base) + 0xc60)
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#define HECI_FWSTS4(base) XE_REG((base) + 0xc64)
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#define HECI_FWSTS5(base) XE_REG((base) + 0xc68)
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#define HECI1_FWSTS5_HUC_AUTH_DONE REG_BIT(19)
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#define HECI_FWSTS6(base) XE_REG((base) + 0xc6c)
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#define HECI_H_GS1(base) XE_REG((base) + 0xc4c)
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#define HECI_H_GS1_ER_PREP REG_BIT(0)
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#define GSCI_TIMER_STATUS XE_REG(0x11ca28)
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#define GSCI_TIMER_STATUS_VALUE REG_GENMASK(1, 0)
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#define GSCI_TIMER_STATUS_RESET_IN_PROGRESS 0
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#define GSCI_TIMER_STATUS_TIMER_EXPIRED 1
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#define GSCI_TIMER_STATUS_RESET_COMPLETE 2
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#define GSCI_TIMER_STATUS_OUT_OF_RESET 3
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#endif
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