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f0c06677d1
The key termination is done with a specific submission to the VCS engine. This flow will be triggered in response to a termination interrupt, whose handling is coming in a follow-up patch in the series. v2: clean up defines and command emission code. (John) Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250129174140.948829-4-daniele.ceraolospurio@intel.com
36 lines
1.2 KiB
C
36 lines
1.2 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_INSTR_DEFS_H_
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#define _XE_INSTR_DEFS_H_
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#include "regs/xe_reg_defs.h"
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/*
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* The first dword of any GPU instruction is the "instruction header." Bits
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* 31:29 identify the general type of the command and determine how exact
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* opcodes and sub-opcodes will be encoded in the remaining bits.
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*/
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#define XE_INSTR_CMD_TYPE GENMASK(31, 29)
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#define XE_INSTR_MI REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x0)
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#define XE_INSTR_GSC REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x2)
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#define XE_INSTR_VIDEOPIPE REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x3)
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#define XE_INSTR_GFXPIPE REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x3)
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#define XE_INSTR_GFX_STATE REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x4)
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/*
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* Most (but not all) instructions have a "length" field in the instruction
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* header. The value expected is the total number of dwords for the
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* instruction, minus two.
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*
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* Some instructions have length fields longer or shorter than 8 bits, but
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* those are rare. This definition can be used for the common case where
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* the length field is from 7:0.
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*/
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#define XE_INSTR_LEN_MASK GENMASK(7, 0)
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#define XE_INSTR_NUM_DW(x) REG_FIELD_PREP(XE_INSTR_LEN_MASK, (x) - 2)
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#endif
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