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Historically, the Vertex Fetcher unit has not been an L3 client. That meant that, when a buffer containing vertex data was written to, it was necessary to issue a PIPE_CONTROL::VF Cache Invalidate to invalidate any VF L2 cachelines associated with that buffer, so the new value would be properly read from memory. Since Tigerlake and later, VERTEX_BUFFER_STATE and 3DSTATE_INDEX_BUFFER have included an "L3 Bypass Enable" bit which userspace drivers can set to request that the vertex fetcher unit snoop L3. However, unlike most true L3 clients, the "VF Cache Invalidate" bit continues to only invalidate the VF L2 cache - and not any associated L3 lines. To handle that, PIPE_CONTROL has a new "L3 Read Only Cache Invalidation Bit", which according to the docs, "controls the invalidation of the Geometry streams cached in L3 cache at the top of the pipe." In other words, the vertex and index buffer data that gets cached in L3 when "L3 Bypass Disable" is set. Mesa always sets L3 Bypass Disable so that the VF unit snoops L3, and whenever it issues a VF Cache Invalidate, it also issues a L3 Read Only Cache Invalidate so that both L2 and L3 vertex data is invalidated. xe is issuing VF cache invalidates too (which handles cases like CPU writes to a buffer between GPU batches). Because userspace may enable L3 snooping, it needs to issue an L3 Read Only Cache Invalidate as well. Fixes significant flickering in Firefox on Meteorlake, which was writing to vertex buffers via the CPU between batches; the missing L3 Read Only invalidates were causing the vertex fetcher to read stale data from L3. Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/4460 Fixes:6ef3bb6055("drm/xe: enable lite restore") Cc: stable@vger.kernel.org # v6.13+ Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://lore.kernel.org/r/20250330165923.56410-1-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (cherry picked from commit61672806b5) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
72 lines
2.8 KiB
C
72 lines
2.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_GPU_COMMANDS_H_
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#define _XE_GPU_COMMANDS_H_
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#include "regs/xe_reg_defs.h"
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#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
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#define SRC_ACCESS_TYPE_SHIFT 21
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#define DST_ACCESS_TYPE_SHIFT 20
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#define CCS_SIZE_MASK GENMASK(17, 8)
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#define XE2_CCS_SIZE_MASK GENMASK(18, 9)
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#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 26)
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#define XE2_XY_CTRL_SURF_MOCS_INDEX_MASK GENMASK(31, 28)
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#define NUM_CCS_BYTES_PER_BLOCK 256
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#define NUM_BYTES_PER_CCS_BYTE(_xe) (GRAPHICS_VER(_xe) >= 20 ? 512 : 256)
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#define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22)
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#define XY_FAST_COLOR_BLT_DEPTH_32 (2 << 19)
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#define XY_FAST_COLOR_BLT_DW 16
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#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 22)
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#define XE2_XY_FAST_COLOR_BLT_MOCS_INDEX_MASK GENMASK(27, 24)
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#define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
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#define XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
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#define XY_FAST_COPY_BLT_DEPTH_32 (3<<24)
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#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)
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#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
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#define XE2_XY_FAST_COPY_BLT_MOCS_INDEX_MASK GENMASK(23, 20)
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#define PVC_MEM_SET_CMD (2 << 29 | 0x5b << 22)
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#define PVC_MEM_SET_CMD_LEN_DW 7
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#define PVC_MEM_SET_MATRIX REG_BIT(17)
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#define PVC_MEM_SET_DATA_FIELD GENMASK(31, 24)
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/* Bspec lists field as [6:0], but index alone is from [6:1] */
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#define PVC_MEM_SET_MOCS_INDEX_MASK GENMASK(6, 1)
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#define XE2_MEM_SET_MOCS_INDEX_MASK GENMASK(6, 3)
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#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
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#define PIPE_CONTROL0_L3_READ_ONLY_CACHE_INVALIDATE BIT(10) /* gen12 */
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#define PIPE_CONTROL0_HDC_PIPELINE_FLUSH BIT(9) /* gen12 */
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#define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29)
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#define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28)
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#define PIPE_CONTROL_AMFS_FLUSH (1<<25)
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#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24)
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#define PIPE_CONTROL_LRI_POST_SYNC BIT(23)
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#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
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#define PIPE_CONTROL_CS_STALL (1<<20)
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#define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET (1<<19)
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#define PIPE_CONTROL_TLB_INVALIDATE BIT(18)
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#define PIPE_CONTROL_PSD_SYNC (1<<17)
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#define PIPE_CONTROL_QW_WRITE (1<<14)
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#define PIPE_CONTROL_DEPTH_STALL (1<<13)
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#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12)
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#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11)
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#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10)
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#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
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#define PIPE_CONTROL_FLUSH_ENABLE (1<<7)
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#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
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#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
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#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
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#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
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#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
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#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
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#endif
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