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The command streamer implements an Arithmetic Logic Unit (ALU) which supports basic arithmetic and logical operations on two 64-bit operands. Access to this ALU is thru the MI_MATH command and sixteen General Purpose Register (GPR) 64-bit registers, which are used as temporary storage. Bspec: 45737, 60236 # MI Bspec: 45525, 60132 # ALU Bspec: 45533, 60309 # GPR Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250304162307.1866-1-michal.wajdeczko@intel.com
80 lines
2.8 KiB
C
80 lines
2.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2025 Intel Corporation
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*/
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#ifndef _XE_ALU_COMMANDS_H_
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#define _XE_ALU_COMMANDS_H_
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#include "instructions/xe_instr_defs.h"
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/* Instruction Opcodes */
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#define CS_ALU_OPCODE_NOOP 0x000
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#define CS_ALU_OPCODE_FENCE_RD 0x001
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#define CS_ALU_OPCODE_FENCE_WR 0x002
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#define CS_ALU_OPCODE_LOAD 0x080
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#define CS_ALU_OPCODE_LOADINV 0x480
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#define CS_ALU_OPCODE_LOAD0 0x081
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#define CS_ALU_OPCODE_LOAD1 0x481
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#define CS_ALU_OPCODE_LOADIND 0x082
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#define CS_ALU_OPCODE_ADD 0x100
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#define CS_ALU_OPCODE_SUB 0x101
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#define CS_ALU_OPCODE_AND 0x102
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#define CS_ALU_OPCODE_OR 0x103
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#define CS_ALU_OPCODE_XOR 0x104
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#define CS_ALU_OPCODE_SHL 0x105
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#define CS_ALU_OPCODE_SHR 0x106
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#define CS_ALU_OPCODE_SAR 0x107
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#define CS_ALU_OPCODE_STORE 0x180
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#define CS_ALU_OPCODE_STOREINV 0x580
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#define CS_ALU_OPCODE_STOREIND 0x181
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/* Instruction Operands */
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#define CS_ALU_OPERAND_REG(n) REG_FIELD_PREP(GENMASK(3, 0), (n))
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#define CS_ALU_OPERAND_REG0 0x0
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#define CS_ALU_OPERAND_REG1 0x1
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#define CS_ALU_OPERAND_REG2 0x2
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#define CS_ALU_OPERAND_REG3 0x3
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#define CS_ALU_OPERAND_REG4 0x4
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#define CS_ALU_OPERAND_REG5 0x5
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#define CS_ALU_OPERAND_REG6 0x6
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#define CS_ALU_OPERAND_REG7 0x7
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#define CS_ALU_OPERAND_REG8 0x8
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#define CS_ALU_OPERAND_REG9 0x9
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#define CS_ALU_OPERAND_REG10 0xa
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#define CS_ALU_OPERAND_REG11 0xb
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#define CS_ALU_OPERAND_REG12 0xc
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#define CS_ALU_OPERAND_REG13 0xd
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#define CS_ALU_OPERAND_REG14 0xe
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#define CS_ALU_OPERAND_REG15 0xf
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#define CS_ALU_OPERAND_SRCA 0x20
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#define CS_ALU_OPERAND_SRCB 0x21
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#define CS_ALU_OPERAND_ACCU 0x31
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#define CS_ALU_OPERAND_ZF 0x32
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#define CS_ALU_OPERAND_CF 0x33
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#define CS_ALU_OPERAND_NA 0 /* N/A operand */
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/* Command Streamer ALU Instructions */
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#define CS_ALU_INSTR(opcode, op1, op2) (REG_FIELD_PREP(GENMASK(31, 20), (opcode)) | \
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REG_FIELD_PREP(GENMASK(19, 10), (op1)) | \
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REG_FIELD_PREP(GENMASK(9, 0), (op2)))
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#define __CS_ALU_INSTR(opcode, op1, op2) CS_ALU_INSTR(CS_ALU_OPCODE_##opcode, \
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CS_ALU_OPERAND_##op1, \
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CS_ALU_OPERAND_##op2)
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#define CS_ALU_INSTR_NOOP __CS_ALU_INSTR(NOOP, NA, NA)
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#define CS_ALU_INSTR_LOAD(op1, op2) __CS_ALU_INSTR(LOAD, op1, op2)
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#define CS_ALU_INSTR_LOADINV(op1, op2) __CS_ALU_INSTR(LOADINV, op1, op2)
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#define CS_ALU_INSTR_LOAD0(op1) __CS_ALU_INSTR(LOAD0, op1, NA)
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#define CS_ALU_INSTR_LOAD1(op1) __CS_ALU_INSTR(LOAD1, op1, NA)
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#define CS_ALU_INSTR_ADD __CS_ALU_INSTR(ADD, NA, NA)
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#define CS_ALU_INSTR_SUB __CS_ALU_INSTR(SUB, NA, NA)
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#define CS_ALU_INSTR_AND __CS_ALU_INSTR(AND, NA, NA)
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#define CS_ALU_INSTR_OR __CS_ALU_INSTR(OR, NA, NA)
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#define CS_ALU_INSTR_XOR __CS_ALU_INSTR(XOR, NA, NA)
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#define CS_ALU_INSTR_STORE(op1, op2) __CS_ALU_INSTR(STORE, op1, op2)
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#define CS_ALU_INSTR_STOREINV(op1, op2) __CS_ALU_INSTR(STOREINV, op1, op2)
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#endif
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