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The LCD controller is composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). It has DPI/DSI interfaces and supports a maximum resolution of 1080p along with 2 RPFs to support the blending of two picture layers and raster operations (ROPs). The DU module is connected to VSPD. Add RZ/G2L DU support for RZ/G2L alike SoCs. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20240218164840.57662-4-biju.das.jz@bp.renesas.com Signed-off-by: Maxime Ripard <mripard@kernel.org>
33 lines
708 B
C
33 lines
708 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* RZ/G2L Display Unit Encoder
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*
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* Copyright (C) 2023 Renesas Electronics Corporation
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*
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* Based on rcar_du_encoder.h
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*/
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#ifndef __RZG2L_DU_ENCODER_H__
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#define __RZG2L_DU_ENCODER_H__
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#include <drm/drm_encoder.h>
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#include <linux/container_of.h>
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struct rzg2l_du_device;
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struct rzg2l_du_encoder {
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struct drm_encoder base;
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enum rzg2l_du_output output;
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};
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static inline struct rzg2l_du_encoder *to_rzg2l_encoder(struct drm_encoder *e)
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{
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return container_of(e, struct rzg2l_du_encoder, base);
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}
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int rzg2l_du_encoder_init(struct rzg2l_du_device *rcdu,
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enum rzg2l_du_output output,
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struct device_node *enc_node);
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#endif /* __RZG2L_DU_ENCODER_H__ */
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