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The clock tree of K1 SoC contains three main types of clock hardware (PLL/DDN/MIX) and has control registers split into several multifunction devices: APBS (PLLs), MPMU, APBC and APMU. All register operations are done through regmap to ensure atomicity between concurrent operations of clock driver and reset, power-domain driver that will be introduced in the future. Signed-off-by: Haylen Chu <heylenay@4d2.org> Reviewed-by: Alex Elder <elder@riscstar.com> Reviewed-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250416135406.16284-4-heylenay@4d2.org Signed-off-by: Yixun Lan <dlan@gentoo.org>
84 lines
2.1 KiB
C
84 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2024 SpacemiT Technology Co. Ltd
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* Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org>
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*
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* DDN stands for "Divider Denominator Numerator", it's M/N clock with a
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* constant x2 factor. This clock hardware follows the equation below,
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*
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* numerator Fin
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* 2 * ------------- = -------
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* denominator Fout
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*
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* Thus, Fout could be calculated with,
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*
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* Fin denominator
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* Fout = ----- * -------------
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* 2 numerator
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*/
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#include <linux/clk-provider.h>
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#include <linux/rational.h>
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#include "ccu_ddn.h"
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static unsigned long ccu_ddn_calc_rate(unsigned long prate,
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unsigned long num, unsigned long den)
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{
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return prate * den / 2 / num;
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}
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static unsigned long ccu_ddn_calc_best_rate(struct ccu_ddn *ddn,
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unsigned long rate, unsigned long prate,
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unsigned long *num, unsigned long *den)
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{
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rational_best_approximation(rate, prate / 2,
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ddn->den_mask >> ddn->den_shift,
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ddn->num_mask >> ddn->num_shift,
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den, num);
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return ccu_ddn_calc_rate(prate, *num, *den);
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}
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static long ccu_ddn_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
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unsigned long num, den;
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return ccu_ddn_calc_best_rate(ddn, rate, *prate, &num, &den);
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}
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static unsigned long ccu_ddn_recalc_rate(struct clk_hw *hw, unsigned long prate)
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{
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struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
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unsigned int val, num, den;
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val = ccu_read(&ddn->common, ctrl);
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num = (val & ddn->num_mask) >> ddn->num_shift;
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den = (val & ddn->den_mask) >> ddn->den_shift;
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return ccu_ddn_calc_rate(prate, num, den);
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}
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static int ccu_ddn_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long prate)
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{
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struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
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unsigned long num, den;
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ccu_ddn_calc_best_rate(ddn, rate, prate, &num, &den);
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ccu_update(&ddn->common, ctrl,
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ddn->num_mask | ddn->den_mask,
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(num << ddn->num_shift) | (den << ddn->den_shift));
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return 0;
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}
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const struct clk_ops spacemit_ccu_ddn_ops = {
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.recalc_rate = ccu_ddn_recalc_rate,
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.round_rate = ccu_ddn_round_rate,
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.set_rate = ccu_ddn_set_rate,
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};
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