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c939154e84
Some PLLS with fractional multipliers have fractional denominators with fixed values, instead of the previous "(1 << pll-> frc.width)". Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20240909-fix_clk-v3-1-a6d8f6333c04@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
55 lines
1.1 KiB
C
55 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#ifndef __MESON_CLK_PLL_H
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#define __MESON_CLK_PLL_H
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include "parm.h"
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struct pll_params_table {
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unsigned int m;
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unsigned int n;
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};
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struct pll_mult_range {
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unsigned int min;
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unsigned int max;
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};
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#define PLL_PARAMS(_m, _n) \
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{ \
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.m = (_m), \
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.n = (_n), \
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}
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#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
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#define CLK_MESON_PLL_NOINIT_ENABLED BIT(1)
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struct meson_clk_pll_data {
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struct parm en;
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struct parm m;
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struct parm n;
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struct parm frac;
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struct parm l;
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struct parm rst;
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struct parm current_en;
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struct parm l_detect;
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const struct reg_sequence *init_regs;
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unsigned int init_count;
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const struct pll_params_table *table;
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const struct pll_mult_range *range;
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unsigned int frac_max;
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u8 flags;
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};
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extern const struct clk_ops meson_clk_pll_ro_ops;
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extern const struct clk_ops meson_clk_pll_ops;
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extern const struct clk_ops meson_clk_pcie_pll_ops;
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#endif /* __MESON_CLK_PLL_H */
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