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5e162f872d
Send JSM state dump message at the beginning of TDR handler. This allows FW to collect debug info in the FW log before the state of the NPU is lost allowing to analyze the cause of a TDR. Wait a predefined timeout (10 ms) so the FW has a chance to write debug logs. We cannot wait for JSM response at this point because IRQs are already disabled before TDR handler is invoked. Signed-off-by: Tomasz Rusinowicz <tomasz.rusinowicz@intel.com> Reviewed-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240930195322.461209-9-jacek.lawrynowicz@linux.intel.com Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
49 lines
2.5 KiB
C
49 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020-2024 Intel Corporation
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*/
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#ifndef __IVPU_JSM_MSG_H__
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#define __IVPU_JSM_MSG_H__
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#include "vpu_jsm_api.h"
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const char *ivpu_jsm_msg_type_to_str(enum vpu_ipc_msg_type type);
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int ivpu_jsm_register_db(struct ivpu_device *vdev, u32 ctx_id, u32 db_id,
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u64 jobq_base, u32 jobq_size);
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int ivpu_jsm_unregister_db(struct ivpu_device *vdev, u32 db_id);
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int ivpu_jsm_get_heartbeat(struct ivpu_device *vdev, u32 engine, u64 *heartbeat);
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int ivpu_jsm_reset_engine(struct ivpu_device *vdev, u32 engine);
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int ivpu_jsm_preempt_engine(struct ivpu_device *vdev, u32 engine, u32 preempt_id);
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int ivpu_jsm_dyndbg_control(struct ivpu_device *vdev, char *command, size_t size);
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int ivpu_jsm_trace_get_capability(struct ivpu_device *vdev, u32 *trace_destination_mask,
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u64 *trace_hw_component_mask);
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int ivpu_jsm_trace_set_config(struct ivpu_device *vdev, u32 trace_level, u32 trace_destination_mask,
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u64 trace_hw_component_mask);
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int ivpu_jsm_context_release(struct ivpu_device *vdev, u32 host_ssid);
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int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev);
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int ivpu_jsm_hws_create_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_group, u32 cmdq_id,
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u32 pid, u32 engine, u64 cmdq_base, u32 cmdq_size);
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int ivpu_jsm_hws_destroy_cmdq(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id);
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int ivpu_jsm_hws_register_db(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id, u32 db_id,
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u64 cmdq_base, u32 cmdq_size);
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int ivpu_jsm_hws_resume_engine(struct ivpu_device *vdev, u32 engine);
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int ivpu_jsm_hws_set_context_sched_properties(struct ivpu_device *vdev, u32 ctx_id, u32 cmdq_id,
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u32 priority);
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int ivpu_jsm_hws_set_scheduling_log(struct ivpu_device *vdev, u32 engine_idx, u32 host_ssid,
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u64 vpu_log_buffer_va);
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int ivpu_jsm_hws_setup_priority_bands(struct ivpu_device *vdev);
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int ivpu_jsm_metric_streamer_start(struct ivpu_device *vdev, u64 metric_group_mask,
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u64 sampling_rate, u64 buffer_addr, u64 buffer_size);
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int ivpu_jsm_metric_streamer_stop(struct ivpu_device *vdev, u64 metric_group_mask);
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int ivpu_jsm_metric_streamer_update(struct ivpu_device *vdev, u64 metric_group_mask,
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u64 buffer_addr, u64 buffer_size, u64 *bytes_written);
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int ivpu_jsm_metric_streamer_info(struct ivpu_device *vdev, u64 metric_group_mask, u64 buffer_addr,
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u64 buffer_size, u32 *sample_size, u64 *info_size);
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int ivpu_jsm_dct_enable(struct ivpu_device *vdev, u32 active_us, u32 inactive_us);
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int ivpu_jsm_dct_disable(struct ivpu_device *vdev);
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int ivpu_jsm_state_dump(struct ivpu_device *vdev);
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#endif
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