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Both Intel and AMD CPUs support 5-level paging, which is expected to become more widely adopted in the future. All major x86 Linux distributions have the feature enabled. Remove CONFIG_X86_5LEVEL and related #ifdeffery for it to make it more readable. Suggested-by: Borislav Petkov <bp@alien8.de> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: https://lore.kernel.org/r/20250516123306.3812286-4-kirill.shutemov@linux.intel.com
321 lines
8.4 KiB
C
321 lines
8.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* prepare to run common code
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*
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* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
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*/
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/* cpu_feature_enabled() cannot be used this early */
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#define USE_EARLY_PGTABLE_L5
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/percpu.h>
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#include <linux/start_kernel.h>
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#include <linux/io.h>
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#include <linux/memblock.h>
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#include <linux/cc_platform.h>
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#include <linux/pgtable.h>
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#include <asm/asm.h>
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#include <asm/page_64.h>
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#include <asm/processor.h>
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#include <asm/proto.h>
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#include <asm/smp.h>
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#include <asm/setup.h>
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#include <asm/desc.h>
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#include <asm/tlbflush.h>
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#include <asm/sections.h>
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#include <asm/kdebug.h>
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#include <asm/e820/api.h>
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#include <asm/bios_ebda.h>
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#include <asm/bootparam_utils.h>
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#include <asm/microcode.h>
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#include <asm/kasan.h>
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#include <asm/fixmap.h>
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#include <asm/realmode.h>
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#include <asm/extable.h>
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#include <asm/trapnr.h>
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#include <asm/sev.h>
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#include <asm/tdx.h>
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#include <asm/init.h>
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/*
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* Manage page tables very early on.
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*/
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extern pmd_t early_dynamic_pgts[EARLY_DYNAMIC_PAGE_TABLES][PTRS_PER_PMD];
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unsigned int __initdata next_early_pgt;
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SYM_PIC_ALIAS(next_early_pgt);
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pmdval_t early_pmd_flags = __PAGE_KERNEL_LARGE & ~(_PAGE_GLOBAL | _PAGE_NX);
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unsigned int __pgtable_l5_enabled __ro_after_init;
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unsigned int pgdir_shift __ro_after_init = 39;
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EXPORT_SYMBOL(pgdir_shift);
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unsigned int ptrs_per_p4d __ro_after_init = 1;
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EXPORT_SYMBOL(ptrs_per_p4d);
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unsigned long page_offset_base __ro_after_init = __PAGE_OFFSET_BASE_L4;
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EXPORT_SYMBOL(page_offset_base);
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unsigned long vmalloc_base __ro_after_init = __VMALLOC_BASE_L4;
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EXPORT_SYMBOL(vmalloc_base);
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unsigned long vmemmap_base __ro_after_init = __VMEMMAP_BASE_L4;
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EXPORT_SYMBOL(vmemmap_base);
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/* Wipe all early page tables except for the kernel symbol map */
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static void __init reset_early_page_tables(void)
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{
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memset(early_top_pgt, 0, sizeof(pgd_t)*(PTRS_PER_PGD-1));
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next_early_pgt = 0;
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write_cr3(__sme_pa_nodebug(early_top_pgt));
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}
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/* Create a new PMD entry */
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bool __init __early_make_pgtable(unsigned long address, pmdval_t pmd)
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{
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unsigned long physaddr = address - __PAGE_OFFSET;
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pgdval_t pgd, *pgd_p;
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p4dval_t p4d, *p4d_p;
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pudval_t pud, *pud_p;
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pmdval_t *pmd_p;
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/* Invalid address or early pgt is done ? */
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if (physaddr >= MAXMEM || read_cr3_pa() != __pa_nodebug(early_top_pgt))
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return false;
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again:
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pgd_p = &early_top_pgt[pgd_index(address)].pgd;
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pgd = *pgd_p;
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/*
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* The use of __START_KERNEL_map rather than __PAGE_OFFSET here is
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* critical -- __PAGE_OFFSET would point us back into the dynamic
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* range and we might end up looping forever...
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*/
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if (!pgtable_l5_enabled())
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p4d_p = pgd_p;
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else if (pgd)
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p4d_p = (p4dval_t *)((pgd & PTE_PFN_MASK) + __START_KERNEL_map - phys_base);
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else {
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if (next_early_pgt >= EARLY_DYNAMIC_PAGE_TABLES) {
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reset_early_page_tables();
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goto again;
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}
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p4d_p = (p4dval_t *)early_dynamic_pgts[next_early_pgt++];
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memset(p4d_p, 0, sizeof(*p4d_p) * PTRS_PER_P4D);
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*pgd_p = (pgdval_t)p4d_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE;
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}
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p4d_p += p4d_index(address);
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p4d = *p4d_p;
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if (p4d)
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pud_p = (pudval_t *)((p4d & PTE_PFN_MASK) + __START_KERNEL_map - phys_base);
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else {
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if (next_early_pgt >= EARLY_DYNAMIC_PAGE_TABLES) {
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reset_early_page_tables();
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goto again;
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}
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pud_p = (pudval_t *)early_dynamic_pgts[next_early_pgt++];
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memset(pud_p, 0, sizeof(*pud_p) * PTRS_PER_PUD);
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*p4d_p = (p4dval_t)pud_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE;
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}
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pud_p += pud_index(address);
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pud = *pud_p;
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if (pud)
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pmd_p = (pmdval_t *)((pud & PTE_PFN_MASK) + __START_KERNEL_map - phys_base);
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else {
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if (next_early_pgt >= EARLY_DYNAMIC_PAGE_TABLES) {
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reset_early_page_tables();
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goto again;
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}
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pmd_p = (pmdval_t *)early_dynamic_pgts[next_early_pgt++];
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memset(pmd_p, 0, sizeof(*pmd_p) * PTRS_PER_PMD);
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*pud_p = (pudval_t)pmd_p - __START_KERNEL_map + phys_base + _KERNPG_TABLE;
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}
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pmd_p[pmd_index(address)] = pmd;
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return true;
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}
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static bool __init early_make_pgtable(unsigned long address)
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{
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unsigned long physaddr = address - __PAGE_OFFSET;
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pmdval_t pmd;
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pmd = (physaddr & PMD_MASK) + early_pmd_flags;
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return __early_make_pgtable(address, pmd);
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}
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void __init do_early_exception(struct pt_regs *regs, int trapnr)
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{
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if (trapnr == X86_TRAP_PF &&
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early_make_pgtable(native_read_cr2()))
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return;
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if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT) &&
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trapnr == X86_TRAP_VC && handle_vc_boot_ghcb(regs))
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return;
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if (trapnr == X86_TRAP_VE && tdx_early_handle_ve(regs))
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return;
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early_fixup_exception(regs, trapnr);
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}
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/* Don't add a printk in there. printk relies on the PDA which is not initialized
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yet. */
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void __init clear_bss(void)
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{
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memset(__bss_start, 0,
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(unsigned long) __bss_stop - (unsigned long) __bss_start);
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memset(__brk_base, 0,
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(unsigned long) __brk_limit - (unsigned long) __brk_base);
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}
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static unsigned long get_cmd_line_ptr(void)
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{
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unsigned long cmd_line_ptr = boot_params.hdr.cmd_line_ptr;
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cmd_line_ptr |= (u64)boot_params.ext_cmd_line_ptr << 32;
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return cmd_line_ptr;
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}
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static void __init copy_bootdata(char *real_mode_data)
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{
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char * command_line;
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unsigned long cmd_line_ptr;
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/*
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* If SME is active, this will create decrypted mappings of the
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* boot data in advance of the copy operations.
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*/
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sme_map_bootdata(real_mode_data);
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memcpy(&boot_params, real_mode_data, sizeof(boot_params));
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sanitize_boot_params(&boot_params);
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cmd_line_ptr = get_cmd_line_ptr();
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if (cmd_line_ptr) {
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command_line = __va(cmd_line_ptr);
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memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
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}
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/*
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* The old boot data is no longer needed and won't be reserved,
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* freeing up that memory for use by the system. If SME is active,
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* we need to remove the mappings that were created so that the
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* memory doesn't remain mapped as decrypted.
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*/
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sme_unmap_bootdata(real_mode_data);
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}
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asmlinkage __visible void __init __noreturn x86_64_start_kernel(char * real_mode_data)
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{
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/*
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* Build-time sanity checks on the kernel image and module
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* area mappings. (these are purely build-time and produce no code)
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*/
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BUILD_BUG_ON(MODULES_VADDR < __START_KERNEL_map);
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BUILD_BUG_ON(MODULES_VADDR - __START_KERNEL_map < KERNEL_IMAGE_SIZE);
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BUILD_BUG_ON(MODULES_LEN + KERNEL_IMAGE_SIZE > 2*PUD_SIZE);
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BUILD_BUG_ON((__START_KERNEL_map & ~PMD_MASK) != 0);
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BUILD_BUG_ON((MODULES_VADDR & ~PMD_MASK) != 0);
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BUILD_BUG_ON(!(MODULES_VADDR > __START_KERNEL));
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MAYBE_BUILD_BUG_ON(!(((MODULES_END - 1) & PGDIR_MASK) ==
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(__START_KERNEL & PGDIR_MASK)));
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BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses) <= MODULES_END);
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cr4_init_shadow();
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/* Kill off the identity-map trampoline */
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reset_early_page_tables();
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if (pgtable_l5_enabled()) {
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page_offset_base = __PAGE_OFFSET_BASE_L5;
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vmalloc_base = __VMALLOC_BASE_L5;
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vmemmap_base = __VMEMMAP_BASE_L5;
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}
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clear_bss();
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/*
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* This needs to happen *before* kasan_early_init() because latter maps stuff
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* into that page.
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*/
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clear_page(init_top_pgt);
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/*
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* SME support may update early_pmd_flags to include the memory
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* encryption mask, so it needs to be called before anything
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* that may generate a page fault.
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*/
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sme_early_init();
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kasan_early_init();
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/*
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* Flush global TLB entries which could be left over from the trampoline page
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* table.
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*
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* This needs to happen *after* kasan_early_init() as KASAN-enabled .configs
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* instrument native_write_cr4() so KASAN must be initialized for that
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* instrumentation to work.
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*/
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__native_tlb_flush_global(this_cpu_read(cpu_tlbstate.cr4));
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idt_setup_early_handler();
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/* Needed before cc_platform_has() can be used for TDX */
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tdx_early_init();
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copy_bootdata(__va(real_mode_data));
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/*
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* Load microcode early on BSP.
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*/
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load_ucode_bsp();
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/* set init_top_pgt kernel high mapping*/
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init_top_pgt[511] = early_top_pgt[511];
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x86_64_start_reservations(real_mode_data);
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}
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void __init __noreturn x86_64_start_reservations(char *real_mode_data)
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{
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/* version is always not zero if it is copied */
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if (!boot_params.hdr.version)
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copy_bootdata(__va(real_mode_data));
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x86_early_init_platform_quirks();
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switch (boot_params.hdr.hardware_subarch) {
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case X86_SUBARCH_INTEL_MID:
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x86_intel_mid_early_setup();
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break;
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default:
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break;
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}
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start_kernel();
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}
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void early_setup_idt(void)
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{
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void *handler = NULL;
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if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) {
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setup_ghcb();
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handler = vc_boot_ghcb;
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}
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startup_64_load_idt(handler);
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}
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