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5a67da1f49
The 5-level paging trampoline is used by both the EFI stub and the traditional decompressor. Move it out of the decompressor sources into the newly minted arch/x86/boot/startup/ sub-directory which will hold startup code that may be shared between the decompressor, the EFI stub and the kernel proper, and needs to tolerate being called during early boot, before the kernel virtual mapping has been created. This will allow the 5-level paging trampoline to be used by EFI boot images such as zboot that omit the traditional decompressor entirely. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: David Woodhouse <dwmw@amazon.co.uk> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Kees Cook <keescook@chromium.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: https://lore.kernel.org/r/20250401133416.1436741-10-ardb+git@google.com
112 lines
2.9 KiB
ArmAsm
112 lines
2.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/boot.h>
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#include <asm/msr.h>
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#include <asm/processor-flags.h>
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/*
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* This is the 32-bit trampoline that will be copied over to low memory. It
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* will be called using the ordinary 64-bit calling convention from code
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* running in 64-bit mode.
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*
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* Return address is at the top of the stack (might be above 4G).
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* The first argument (EDI) contains the address of the temporary PGD level
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* page table in 32-bit addressable memory which will be programmed into
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* register CR3.
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*/
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.section ".rodata", "a", @progbits
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SYM_CODE_START(trampoline_32bit_src)
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/*
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* Preserve callee save 64-bit registers on the stack: this is
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* necessary because the architecture does not guarantee that GPRs will
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* retain their full 64-bit values across a 32-bit mode switch.
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*/
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pushq %r15
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pushq %r14
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pushq %r13
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pushq %r12
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pushq %rbp
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pushq %rbx
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/* Preserve top half of RSP in a legacy mode GPR to avoid truncation */
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movq %rsp, %rbx
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shrq $32, %rbx
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/* Switch to compatibility mode (CS.L = 0 CS.D = 1) via far return */
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pushq $__KERNEL32_CS
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leaq 0f(%rip), %rax
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pushq %rax
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lretq
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/*
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* The 32-bit code below will do a far jump back to long mode and end
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* up here after reconfiguring the number of paging levels. First, the
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* stack pointer needs to be restored to its full 64-bit value before
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* the callee save register contents can be popped from the stack.
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*/
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.Lret:
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shlq $32, %rbx
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orq %rbx, %rsp
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/* Restore the preserved 64-bit registers */
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popq %rbx
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popq %rbp
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popq %r12
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popq %r13
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popq %r14
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popq %r15
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retq
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.code32
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0:
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/* Disable paging */
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movl %cr0, %eax
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btrl $X86_CR0_PG_BIT, %eax
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movl %eax, %cr0
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/* Point CR3 to the trampoline's new top level page table */
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movl %edi, %cr3
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/* Set EFER.LME=1 as a precaution in case hypervsior pulls the rug */
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movl $MSR_EFER, %ecx
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rdmsr
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btsl $_EFER_LME, %eax
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/* Avoid writing EFER if no change was made (for TDX guest) */
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jc 1f
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wrmsr
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1:
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/* Toggle CR4.LA57 */
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movl %cr4, %eax
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btcl $X86_CR4_LA57_BIT, %eax
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movl %eax, %cr4
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/* Enable paging again. */
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movl %cr0, %eax
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btsl $X86_CR0_PG_BIT, %eax
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movl %eax, %cr0
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/*
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* Return to the 64-bit calling code using LJMP rather than LRET, to
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* avoid the need for a 32-bit addressable stack. The destination
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* address will be adjusted after the template code is copied into a
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* 32-bit addressable buffer.
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*/
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.Ljmp: ljmpl $__KERNEL_CS, $(.Lret - trampoline_32bit_src)
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SYM_CODE_END(trampoline_32bit_src)
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/*
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* This symbol is placed right after trampoline_32bit_src() so its address can
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* be used to infer the size of the trampoline code.
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*/
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SYM_DATA(trampoline_ljmp_imm_offset, .word .Ljmp + 1 - trampoline_32bit_src)
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/*
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* The trampoline code has a size limit.
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* Make sure we fail to compile if the trampoline code grows
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* beyond TRAMPOLINE_32BIT_CODE_SIZE bytes.
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*/
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.org trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_SIZE
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