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RISC-V APLIC specification defines "hart index" in [1]. Similar definitions can be found for ACLINT in [2] Quote from the APLIC specification: Within a given interrupt domain, each of the domain’s harts has a unique index number in the range 0 to 2^14 − 1 (= 16,383). The index number a domain associates with a hart may or may not have any relationship to the unique hart identifier (“hart ID”) that the RISC-V Privileged Architecture assigns to the hart. Two different interrupt domains may employ entirely different index numbers for the same set of harts. Further, it says in "4.5 Memory-mapped control region for an interrupt domain": The array of IDC structures may include some for potential hart index numbers that are not actual hart index numbers in the domain. For example, the first IDC structure is always for hart index 0, but 0 is not necessarily a valid index number for any hart in the domain. Support arbitrary hart indices specified in an optional property "riscv,hart-indexes" which is specified as an array of u32 elements, one per interrupt target, listing hart indexes in the same order as in "interrupts-extended". If this property is not specified, fall back to use logical hart indices within the domain. Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250612143911.3224046-2-vladimir.kondratiev@mobileye.com Link: https://github.com/riscv/riscv-aia [1] Link: https://github.com/riscvarchive/riscv-aclint [2]
151 lines
3.5 KiB
C
151 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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* Copyright (C) 2018 Christoph Hellwig
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*/
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/scs.h>
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#include <linux/seq_file.h>
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#include <asm/sbi.h>
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#include <asm/smp.h>
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#include <asm/softirq_stack.h>
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#include <asm/stacktrace.h>
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static struct fwnode_handle *(*__get_intc_node)(void);
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void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void))
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{
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__get_intc_node = fn;
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}
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struct fwnode_handle *riscv_get_intc_hwnode(void)
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{
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if (__get_intc_node)
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return __get_intc_node();
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return NULL;
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}
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EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode);
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/**
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* riscv_get_hart_index() - get hart index for interrupt delivery
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* @fwnode: interrupt controller node
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* @logical_index: index within the "interrupts-extended" property
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* @hart_index: filled with the hart index to use
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*
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* RISC-V uses term "hart index" for its interrupt controllers, for the
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* purpose of the interrupt routing to destination harts.
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* It may be arbitrary numbers assigned to each destination hart in context
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* of the particular interrupt domain.
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*
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* These numbers encoded in the optional property "riscv,hart-indexes"
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* that should contain hart index for each interrupt destination in the same
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* order as in the "interrupts-extended" property. If this property
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* not exist, it assumed equal to the logical index, i.e. index within the
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* "interrupts-extended" property.
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*
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* Return: error code
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*/
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int riscv_get_hart_index(struct fwnode_handle *fwnode, u32 logical_index,
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u32 *hart_index)
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{
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static const char *prop_hart_index = "riscv,hart-indexes";
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struct device_node *np = to_of_node(fwnode);
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if (!np || !of_property_present(np, prop_hart_index)) {
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*hart_index = logical_index;
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return 0;
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}
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return of_property_read_u32_index(np, prop_hart_index,
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logical_index, hart_index);
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}
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#ifdef CONFIG_IRQ_STACKS
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#include <asm/irq_stack.h>
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DECLARE_PER_CPU(ulong *, irq_shadow_call_stack_ptr);
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#ifdef CONFIG_SHADOW_CALL_STACK
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DEFINE_PER_CPU(ulong *, irq_shadow_call_stack_ptr);
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#endif
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static void init_irq_scs(void)
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{
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int cpu;
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if (!scs_is_enabled())
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return;
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for_each_possible_cpu(cpu)
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per_cpu(irq_shadow_call_stack_ptr, cpu) =
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scs_alloc(cpu_to_node(cpu));
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}
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DEFINE_PER_CPU(ulong *, irq_stack_ptr);
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#ifdef CONFIG_VMAP_STACK
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static void init_irq_stacks(void)
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{
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int cpu;
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ulong *p;
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for_each_possible_cpu(cpu) {
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p = arch_alloc_vmap_stack(IRQ_STACK_SIZE, cpu_to_node(cpu));
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per_cpu(irq_stack_ptr, cpu) = p;
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}
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}
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#else
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/* irq stack only needs to be 16 byte aligned - not IRQ_STACK_SIZE aligned. */
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DEFINE_PER_CPU_ALIGNED(ulong [IRQ_STACK_SIZE/sizeof(ulong)], irq_stack);
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static void init_irq_stacks(void)
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{
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int cpu;
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for_each_possible_cpu(cpu)
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per_cpu(irq_stack_ptr, cpu) = per_cpu(irq_stack, cpu);
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}
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#endif /* CONFIG_VMAP_STACK */
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#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
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static void ___do_softirq(struct pt_regs *regs)
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{
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__do_softirq();
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}
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void do_softirq_own_stack(void)
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{
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if (on_thread_stack())
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call_on_irq_stack(NULL, ___do_softirq);
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else
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__do_softirq();
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}
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#endif /* CONFIG_SOFTIRQ_ON_OWN_STACK */
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#else
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static void init_irq_scs(void) {}
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static void init_irq_stacks(void) {}
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#endif /* CONFIG_IRQ_STACKS */
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
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show_ipi_stats(p, prec);
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return 0;
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}
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void __init init_IRQ(void)
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{
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init_irq_scs();
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init_irq_stacks();
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irqchip_init();
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if (!handle_arch_irq)
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panic("No interrupt controller found.");
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sbi_ipi_init();
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}
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