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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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724ba67515
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
432 lines
11 KiB
Plaintext
432 lines
11 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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//
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// Device Tree Source for UniPhier LD4 SoC
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//
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// Copyright (C) 2015-2016 Socionext Inc.
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// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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#include <dt-bindings/gpio/uniphier-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "socionext,uniphier-ld4";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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clocks {
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refclk: ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24576000>;
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};
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arm_timer_clk: arm-timer {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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l2: cache-controller@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
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<0x506c0000 0x400>;
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
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cache-unified;
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cache-size = <(512 * 1024)>;
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cache-sets = <256>;
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cache-line-size = <128>;
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cache-level = <2>;
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};
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spi: spi@54006000 {
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compatible = "socionext,uniphier-scssi";
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status = "disabled";
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reg = <0x54006000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0>;
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clocks = <&peri_clk 11>;
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resets = <&peri_rst 11>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&peri_clk 0>;
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resets = <&peri_rst 0>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&peri_clk 1>;
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resets = <&peri_rst 1>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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clocks = <&peri_clk 2>;
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resets = <&peri_rst 2>;
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};
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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clocks = <&peri_clk 3>;
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resets = <&peri_rst 3>;
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};
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gpio: gpio@55000000 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000000 0x200>;
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interrupt-parent = <&aidet>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 0>;
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gpio-ranges-group-names = "gpio_range";
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ngpios = <136>;
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socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
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};
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i2c0: i2c@58400000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58400000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&peri_clk 4>;
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resets = <&peri_rst 4>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58480000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58480000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clocks = <&peri_clk 5>;
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resets = <&peri_rst 5>;
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clock-frequency = <100000>;
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};
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/* chip-internal connection for DMD */
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i2c2: i2c@58500000 {
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compatible = "socionext,uniphier-i2c";
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reg = <0x58500000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clocks = <&peri_clk 6>;
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resets = <&peri_rst 6>;
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clock-frequency = <400000>;
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};
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i2c3: i2c@58580000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58580000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clocks = <&peri_clk 7>;
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resets = <&peri_rst 7>;
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clock-frequency = <100000>;
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};
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system_bus: system-bus@58c00000 {
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compatible = "socionext,uniphier-system-bus";
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status = "disabled";
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reg = <0x58c00000 0x400>;
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#address-cells = <2>;
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#size-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_system_bus>;
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};
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smpctrl@59801000 {
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compatible = "socionext,uniphier-smpctrl";
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reg = <0x59801000 0x400>;
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};
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syscon@59810000 {
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compatible = "socionext,uniphier-ld4-mioctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x800>;
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mio_clk: clock-controller {
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compatible = "socionext,uniphier-ld4-mio-clock";
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#clock-cells = <1>;
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};
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mio_rst: reset-controller {
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compatible = "socionext,uniphier-ld4-mio-reset";
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#reset-cells = <1>;
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};
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};
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syscon@59820000 {
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compatible = "socionext,uniphier-ld4-perictrl",
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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peri_clk: clock-controller {
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compatible = "socionext,uniphier-ld4-peri-clock";
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#clock-cells = <1>;
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};
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peri_rst: reset-controller {
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compatible = "socionext,uniphier-ld4-peri-reset";
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#reset-cells = <1>;
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};
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};
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dmac: dma-controller@5a000000 {
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compatible = "socionext,uniphier-mio-dmac";
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reg = <0x5a000000 0x1000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mio_clk 7>;
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resets = <&mio_rst 7>;
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#dma-cells = <1>;
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};
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sd: mmc@5a400000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a400000 0x200>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default", "uhs";
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pinctrl-0 = <&pinctrl_sd>;
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pinctrl-1 = <&pinctrl_sd_uhs>;
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clocks = <&mio_clk 0>;
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reset-names = "host", "bridge";
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resets = <&mio_rst 0>, <&mio_rst 3>;
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dma-names = "rx-tx";
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dmas = <&dmac 4>;
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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};
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emmc: mmc@5a500000 {
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compatible = "socionext,uniphier-sd-v2.91";
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status = "disabled";
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reg = <0x5a500000 0x200>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_emmc>;
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clocks = <&mio_clk 1>;
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reset-names = "host", "bridge", "hw";
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resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
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dma-names = "rx-tx";
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dmas = <&dmac 6>;
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bus-width = <8>;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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non-removable;
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};
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usb0: usb@5a800100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a800100 0x100>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
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<&mio_clk 12>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
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<&mio_rst 12>;
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has-transaction-translator;
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};
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usb1: usb@5a810100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a810100 0x100>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
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<&mio_clk 13>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
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<&mio_rst 13>;
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has-transaction-translator;
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};
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usb2: usb@5a820100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a820100 0x100>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb2>;
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clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
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<&mio_clk 14>;
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resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
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<&mio_rst 14>;
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has-transaction-translator;
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};
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syscon@5f800000 {
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compatible = "socionext,uniphier-ld4-soc-glue",
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"simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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pinctrl: pinctrl {
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compatible = "socionext,uniphier-ld4-pinctrl";
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};
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};
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syscon@5f900000 {
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compatible = "socionext,uniphier-ld4-soc-glue-debug",
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"simple-mfd", "syscon";
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reg = <0x5f900000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x5f900000 0x2000>;
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efuse@100 {
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compatible = "socionext,uniphier-efuse";
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reg = <0x100 0x28>;
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};
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efuse@130 {
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compatible = "socionext,uniphier-efuse";
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reg = <0x130 0x8>;
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};
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};
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timer@60000200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x60000200 0x20>;
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interrupts = <GIC_PPI 11
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(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&arm_timer_clk>;
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};
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timer@60000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x60000600 0x20>;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_RAW(1) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&arm_timer_clk>;
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};
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intc: interrupt-controller@60001000 {
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compatible = "arm,cortex-a9-gic";
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reg = <0x60001000 0x1000>,
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<0x60000100 0x100>;
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#interrupt-cells = <3>;
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interrupt-controller;
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};
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aidet: interrupt-controller@61830000 {
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compatible = "socionext,uniphier-ld4-aidet";
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reg = <0x61830000 0x200>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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syscon@61840000 {
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compatible = "socionext,uniphier-ld4-sysctrl",
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"simple-mfd", "syscon";
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reg = <0x61840000 0x10000>;
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sys_clk: clock-controller {
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compatible = "socionext,uniphier-ld4-clock";
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#clock-cells = <1>;
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};
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sys_rst: reset-controller {
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compatible = "socionext,uniphier-ld4-reset";
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#reset-cells = <1>;
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};
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};
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nand: nand-controller@68000000 {
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compatible = "socionext,uniphier-denali-nand-v5a";
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status = "disabled";
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reg-names = "nand_data", "denali_reg";
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reg = <0x68000000 0x20>, <0x68100000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand>;
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clock-names = "nand", "nand_x", "ecc";
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clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
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reset-names = "nand", "reg";
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resets = <&sys_rst 2>, <&sys_rst 2>;
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};
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};
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};
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#include "uniphier-pinctrl.dtsi"
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