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0cbf959f8d
Use the more concise interrupts-extended property to fully describe the interrupts. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/623645456e7636f43150a70f8603114b26304818.1728045620.git.geert+renesas@glider.be
81 lines
1.4 KiB
Plaintext
81 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the SK-RZG1M board
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*
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* Copyright (C) 2016-2017 Cogent Embedded, Inc.
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*/
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/dts-v1/;
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#include "r8a7743.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "SK-RZG1M";
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compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
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aliases {
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serial0 = &scif0;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
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stdout-path = "serial0:115200n8";
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x40000000>;
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};
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memory@200000000 {
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device_type = "memory";
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reg = <2 0x00000000 0 0x40000000>;
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};
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};
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&extal_clk {
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clock-frequency = <20000000>;
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};
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&pfc {
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scif0_pins: scif0 {
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groups = "scif0_data_d";
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function = "scif0";
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};
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ether_pins: ether {
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groups = "eth_link", "eth_mdio", "eth_rmii";
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function = "eth";
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};
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phy1_pins: phy1 {
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groups = "intc_irq0";
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function = "intc";
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};
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};
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&scif0 {
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pinctrl-0 = <&scif0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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ðer {
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pinctrl-0 = <ðer_pins>, <&phy1_pins>;
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pinctrl-names = "default";
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phy-handle = <&phy1>;
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renesas,ether-link-active-low;
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status = "okay";
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phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id0022.1537",
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"ethernet-phy-ieee802.3-c22";
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reg = <1>;
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interrupts-extended = <&irqc 0 IRQ_TYPE_LEVEL_LOW>;
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micrel,led-mode = <1>;
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reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
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};
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};
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