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c322d10fe5
The watchdog appears to be an ARM SP805, add the full compatible and the needed clocks properties. Leave this disabled for now as functionality is not fully tested. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20240612151314.27967-2-afd@ti.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
223 lines
4.1 KiB
Plaintext
223 lines
4.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,arm926ej-s";
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device_type = "cpu";
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reg = <0>;
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};
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};
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bootrom: bootrom@0 {
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reg = <0x00000000 0x80000>;
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};
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sram: sram@a4000000 {
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compatible = "mmio-sram";
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reg = <0xa4000000 0x20000>; /* 128k */
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xa4000000 0x20000>;
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sram@0 {
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reg = <0x0 0x20000>;
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};
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};
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timer_clk: timer_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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base_clk: base_clk {
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#clock-cells = <0>;
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reg = <0x900b0024 0x4>;
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};
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ahb_clk: ahb_clk {
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#clock-cells = <0>;
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reg = <0x900b0024 0x4>;
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clocks = <&base_clk>;
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};
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apb_pclk: apb_pclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&ahb_clk>;
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};
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usb_phy: usb_phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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vbus_reg: vbus_reg {
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compatible = "regulator-fixed";
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regulator-name = "USB VBUS output";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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spi: spi@a9000000 {
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reg = <0xa9000000 0x1000>;
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};
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usb0: usb@b0000000 {
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compatible = "lsi,zevio-usb";
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reg = <0xb0000000 0x1000>;
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interrupts = <8>;
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usb-phy = <&usb_phy>;
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vbus-supply = <&vbus_reg>;
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};
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usb1: usb@b4000000 {
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reg = <0xb4000000 0x1000>;
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interrupts = <9>;
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status = "disabled";
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};
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lcd: lcd@c0000000 {
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compatible = "arm,pl111", "arm,primecell";
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reg = <0xc0000000 0x1000>;
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interrupts = <21>;
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/*
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* We assume the same clock is fed to APB and CLCDCLK.
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* There is some code to scale the clock down by a factor
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* 48 for the display so likely the frequency to the
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* display is 1MHz and the CLCDCLK is 48 MHz.
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*/
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clocks = <&apb_pclk>, <&apb_pclk>;
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clock-names = "clcdclk", "apb_pclk";
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};
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adc: adc@c4000000 {
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reg = <0xc4000000 0x1000>;
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interrupts = <11>;
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};
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tdes: crypto@c8010000 {
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reg = <0xc8010000 0x1000>;
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};
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sha256: crypto@cc000000 {
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reg = <0xcc000000 0x1000>;
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};
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apb@90000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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clock-ranges;
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ranges;
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gpio: gpio@90000000 {
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compatible = "lsi,zevio-gpio";
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reg = <0x90000000 0x1000>;
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interrupts = <7>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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fast_timer: timer@90010000 {
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reg = <0x90010000 0x1000>;
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interrupts = <17>;
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};
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uart: serial@90020000 {
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reg = <0x90020000 0x1000>;
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interrupts = <1>;
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};
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timer0: timer@900c0000 {
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reg = <0x900c0000 0x1000>;
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clocks = <&timer_clk>, <&timer_clk>,
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<&timer_clk>;
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clock-names = "timer0clk", "timer1clk",
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"apb_pclk";
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};
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timer1: timer@900d0000 {
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reg = <0x900d0000 0x1000>;
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interrupts = <19>;
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clocks = <&timer_clk>, <&timer_clk>,
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<&timer_clk>;
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clock-names = "timer0clk", "timer1clk",
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"apb_pclk";
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};
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watchdog: watchdog@90060000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x90060000 0x1000>;
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interrupts = <3>;
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clocks = <&apb_pclk>, <&apb_pclk>;
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clock-names = "wdog_clk", "apb_pclk";
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status = "disabled";
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};
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rtc: rtc@90090000 {
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reg = <0x90090000 0x1000>;
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interrupts = <4>;
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};
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misc: misc@900a0000 {
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compatible = "ti,nspire-misc", "syscon", "simple-mfd";
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reg = <0x900a0000 0x1000>;
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reboot {
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compatible = "syscon-reboot";
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offset = <0x08>;
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value = <0x02>;
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};
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};
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pwr: pwr@900b0000 {
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reg = <0x900b0000 0x1000>;
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interrupts = <15>;
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};
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keypad: input@900e0000 {
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compatible = "ti,nspire-keypad";
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reg = <0x900e0000 0x1000>;
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interrupts = <16>;
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scan-interval = <1000>;
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row-delay = <200>;
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clocks = <&apb_pclk>;
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};
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contrast: contrast@900f0000 {
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reg = <0x900f0000 0x1000>;
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};
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led: led@90110000 {
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reg = <0x90110000 0x1000>;
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};
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};
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};
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};
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