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4101c8274b
Describe the cache memories according with datasheet chapter 15.2: - L1 cache configuration with 32KB for both data and instruction cache. - L2 cache configuration with 256KB unified cache. Before this patch the kernel reported the warning: [ 0.161955] cacheinfo: Unable to detect cache hierarchy for CPU 0 Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20250619070636.8844-2-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
726 lines
22 KiB
Plaintext
726 lines
22 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC
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*
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* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Ryan Wanner <Ryan.Wanner@microchip.com>
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*
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*/
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/mfd/at91-usart.h>
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/ {
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model = "Microchip SAMA7D65 family SoC";
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compatible = "microchip,sama7d65";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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device_type = "cpu";
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clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
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clock-names = "cpu";
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d-cache-size = <0x8000>; // L1, 32 KB
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i-cache-size = <0x8000>; // L1, 32 KB
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next-level-cache = <&L2>;
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x40000>; // L2, 256 KB
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cache-unified;
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};
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};
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};
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clocks {
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main_xtal: clock-mainxtal {
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compatible = "fixed-clock";
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clock-output-names = "main_xtal";
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#clock-cells = <0>;
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};
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slow_xtal: clock-slowxtal {
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compatible = "fixed-clock";
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clock-output-names = "slow_xtal";
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#clock-cells = <0>;
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};
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};
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ns_sram: sram@100000 {
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compatible = "mmio-sram";
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reg = <0x100000 0x20000>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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soc {
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compatible = "simple-bus";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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securam: sram@e0000800 {
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compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram";
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reg = <0xe0000800 0x4000>;
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ranges = <0 0xe0000800 0x4000>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
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#address-cells = <1>;
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#size-cells = <1>;
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no-memory-wc;
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};
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secumod: security-module@e0004000 {
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compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon";
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reg = <0xe0004000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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sfrbu: sfr@e0008000 {
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compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
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reg = <0xe0008000 0x20>;
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};
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pioa: pinctrl@e0014000 {
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compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl";
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reg = <0xe0014000 0x800>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pmc: clock-controller@e0018000 {
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compatible = "microchip,sama7d65-pmc", "syscon";
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reg = <0xe0018000 0x200>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#clock-cells = <2>;
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clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
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clock-names = "td_slck", "md_slck", "main_xtal";
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};
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ps_wdt: watchdog@e001d000 {
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compatible = "microchip,sama7d65-wdt", "microchip,sama7g5-wdt";
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reg = <0xe001d000 0x30>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk32k 0>;
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};
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reset_controller: reset-controller@e001d100 {
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compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc";
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reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>;
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#reset-cells = <1>;
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clocks = <&clk32k 0>;
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};
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shdwc: poweroff@e001d200 {
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compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon";
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reg = <0xe001d200 0x20>;
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clocks = <&clk32k 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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atmel,wakeup-rtc-timer;
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atmel,wakeup-rtt-timer;
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status = "disabled";
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};
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rtt: rtc@e001d300 {
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compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt";
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reg = <0xe001d300 0x30>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk32k 0>;
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};
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clk32k: clock-controller@e001d500 {
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compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
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reg = <0xe001d500 0x4>;
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clocks = <&slow_xtal>;
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#clock-cells = <1>;
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};
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gpbr: syscon@e001d700 {
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compatible = "microchip,sama7d65-gpbr", "syscon";
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reg = <0xe001d700 0x48>;
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};
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rtc: rtc@e001d800 {
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compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc";
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reg = <0xe001d800 0x30>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk32k 1>;
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};
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chipid@e0020000 {
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compatible = "microchip,sama7d65-chipid";
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reg = <0xe0020000 0x8>;
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};
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can0: can@e0828000 {
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compatible = "bosch,m_can";
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reg = <0xe0828000 0x200>, <0x100000 0x7800>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
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clock-names = "hclk", "cclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 58>;
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assigned-clock-rates = <40000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
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bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
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status = "disabled";
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};
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can1: can@e082c000 {
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compatible = "bosch,m_can";
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reg = <0xe082c000 0x200>, <0x100000 0xbc00>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
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clock-names = "hclk", "cclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 59>;
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assigned-clock-rates = <40000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
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bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
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status = "disabled";
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};
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can2: can@e0830000 {
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compatible = "bosch,m_can";
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reg = <0xe0830000 0x200>, <0x100000 0x10000>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 60>, <&pmc PMC_TYPE_GCK 60>;
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clock-names = "hclk", "cclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 60>;
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assigned-clock-rates = <40000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
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bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
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status = "disabled";
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};
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can3: can@e0834000 {
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compatible = "bosch,m_can";
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reg = <0xe0834000 0x200>, <0x110000 0x4400>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
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clock-names = "hclk", "cclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
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assigned-clock-rates = <40000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
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bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
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status = "disabled";
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};
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can4: can@e0838000 {
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compatible = "bosch,m_can";
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reg = <0xe0838000 0x200>, <0x110000 0x8800>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
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clock-names = "hclk", "cclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
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assigned-clock-rates = <40000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
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bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
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status = "disabled";
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};
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dma2: dma-controller@e1200000 {
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compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
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reg = <0xe1200000 0x1000>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
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clock-names = "dma_clk";
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dma-requests = <0>;
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status = "disabled";
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};
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sdmmc1: mmc@e1208000 {
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compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci";
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reg = <0xe1208000 0x400>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>;
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clock-names = "hclock", "multclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 76>;
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assigned-clock-rates = <200000000>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>;
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status = "disabled";
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};
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aes: crypto@e1600000 {
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compatible = "microchip,sama7d65-aes", "atmel,at91sam9g46-aes";
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reg = <0xe1600000 0x100>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
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clock-names = "aes_clk";
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dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
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<&dma0 AT91_XDMAC_DT_PERID(2)>;
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dma-names = "tx", "rx";
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};
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sha: crypto@e1604000 {
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compatible = "microchip,sama7d65-sha", "atmel,at91sam9g46-sha";
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reg = <0xe1604000 0x100>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 78>;
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clock-names = "sha_clk";
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dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
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dma-names = "tx";
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};
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tdes: crypto@e1608000 {
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compatible = "microchip,sama7d65-tdes", "atmel,at91sam9g46-tdes";
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reg = <0xe1608000 0x100>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 91>;
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clock-names = "tdes_clk";
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dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
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<&dma0 AT91_XDMAC_DT_PERID(53)>;
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dma-names = "tx", "rx";
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};
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trng: rng@e160c000 {
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compatible = "microchip,sama7d65-trng", "microchip,sam9x60-trng";
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reg = <0xe160c000 0x100>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 92>;
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};
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dma0: dma-controller@e1610000 {
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compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
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reg = <0xe1610000 0x1000>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
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clock-names = "dma_clk";
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status = "disabled";
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};
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dma1: dma-controller@e1614000 {
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compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
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reg = <0xe1614000 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
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clock-names = "dma_clk";
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status = "disabled";
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};
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gmac0: ethernet@e1618000 {
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compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem";
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reg = <0xe1618000 0x2000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>;
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clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>;
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assigned-clock-rates = <125000000>, <200000000>;
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status = "disabled";
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};
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gmac1: ethernet@e161c000 {
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compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem";
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reg = <0xe161c000 0x2000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_PERIPHERAL 47>,<&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>;
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clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>;
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assigned-clock-rates = <125000000>, <200000000>;
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status = "disabled";
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};
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pit64b0: timer@e1800000 {
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compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
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reg = <0xe1800000 0x100>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
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clock-names = "pclk", "gclk";
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};
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pit64b1: timer@e1804000 {
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compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b";
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reg = <0xe1804000 0x100>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>;
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clock-names = "pclk", "gclk";
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};
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pwm: pwm@e1818000 {
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compatible = "microchip,sama7d65-pwm", "atmel,sama5d2-pwm";
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reg = <0xe1818000 0x500>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 72>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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flx0: flexcom@e1820000 {
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compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
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reg = <0xe1820000 0x200>;
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ranges = <0x0 0xe1820000 0x800>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
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#address-cells = <1>;
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#size-cells = <1>;
|
|
status = "disabled";
|
|
|
|
uart0: serial@200 {
|
|
compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
|
|
reg = <0x200 0x200>;
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
|
|
clock-names = "usart";
|
|
dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>,
|
|
<&dma1 AT91_XDMAC_DT_PERID(5)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@600 {
|
|
compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
|
|
reg = <0x600 0x200>;
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
atmel,fifo-size = <32>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(6)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(5)>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx1: flexcom@e1824000 {
|
|
compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
|
|
reg = <0xe1824000 0x200>;
|
|
ranges = <0x0 0xe1824000 0x800>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "disabled";
|
|
|
|
spi1: spi@400 {
|
|
compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi";
|
|
reg = <0x400 0x200>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
|
|
clock-names = "spi_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(7)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,fifo-size = <32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@600 {
|
|
compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
|
|
reg = <0x600 0x200>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(7)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,fifo-size = <32>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx2: flexcom@e1828000 {
|
|
compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
|
|
reg = <0xe1828000 0x200>;
|
|
ranges = <0x0 0xe1828000 0x800>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "disabled";
|
|
|
|
uart2: serial@200 {
|
|
compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
|
|
reg = <0x200 0x200>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
|
|
clock-names = "usart";
|
|
dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>,
|
|
<&dma1 AT91_XDMAC_DT_PERID(9)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx3: flexcom@e182c000 {
|
|
compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
|
|
reg = <0xe182c000 0x200>;
|
|
ranges = <0x0 0xe182c000 0x800>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "disabled";
|
|
|
|
i2c3: i2c@600 {
|
|
compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
|
|
reg = <0x600 0x200>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(11)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,fifo-size = <32>;
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|
|
|
|
flx4: flexcom@e2018000 {
|
|
compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
|
|
reg = <0xe2018000 0x200>;
|
|
ranges = <0x0 0xe2018000 0x800>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "disabled";
|
|
|
|
uart4: serial@200 {
|
|
compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
|
|
reg = <0x200 0x200>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
|
|
clock-names = "usart";
|
|
dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>,
|
|
<&dma1 AT91_XDMAC_DT_PERID(13)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
atmel,fifo-size = <16>;
|
|
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi4: spi@400 {
|
|
compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi";
|
|
reg = <0x400 0x200>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
|
|
clock-names = "spi_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(13)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,fifo-size = <32>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx5: flexcom@e201c000 {
|
|
compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
|
|
reg = <0xe201c000 0x200>;
|
|
ranges = <0x0 0xe201c000 0x800>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "disabled";
|
|
|
|
i2c5: i2c@600 {
|
|
compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
|
|
reg = <0x600 0x200>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(15)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,fifo-size = <32>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx6: flexcom@e2020000 {
|
|
compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
|
|
reg = <0xe2020000 0x200>;
|
|
ranges = <0x0 0xe2020000 0x800>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
|
|
status = "disabled";
|
|
|
|
uart6: serial@200 {
|
|
compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
|
|
reg = <0x200 0x200>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
|
|
clock-names = "usart";
|
|
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
|
atmel,fifo-size = <16>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx7: flexcom@e2024000 {
|
|
compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
|
|
reg = <0xe2024000 0x200>;
|
|
ranges = <0x0 0xe2024000 0x800>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "disabled";
|
|
|
|
uart7: serial@200 {
|
|
compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart";
|
|
reg = <0x200 0x200>;
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
|
|
clock-names = "usart";
|
|
dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>,
|
|
<&dma1 AT91_XDMAC_DT_PERID(19)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
atmel,fifo-size = <16>;
|
|
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx8: flexcom@e281c000 {
|
|
compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
|
|
reg = <0xe281c000 0x200>;
|
|
ranges = <0x0 0xe281c000 0x800>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "disabled";
|
|
|
|
i2c8: i2c@600 {
|
|
compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
|
|
reg = <0x600 0x200>;
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(21)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,fifo-size = <32>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx9: flexcom@e2820000 {
|
|
compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
|
|
reg = <0xe2820000 0x200>;
|
|
ranges = <0x0 0xe281c000 0x800>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "disabled";
|
|
|
|
i2c9: i2c@600 {
|
|
compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
|
|
reg = <0x600 0x200>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(23)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,fifo-size = <32>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx10: flexcom@e2824000 {
|
|
compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom";
|
|
reg = <0xe2824000 0x200>;
|
|
ranges = <0x0 0xe2824000 0x800>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "disabled";
|
|
|
|
i2c10: i2c@600 {
|
|
compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c";
|
|
reg = <0x600 0x200>;
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
atmel,fifo-size = <32>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
uddrc: uddrc@e3800000 {
|
|
compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc";
|
|
reg = <0xe3800000 0x4000>;
|
|
};
|
|
|
|
ddr3phy: ddr3phy@e3804000 {
|
|
compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy";
|
|
reg = <0xe3804000 0x1000>;
|
|
};
|
|
|
|
gic: interrupt-controller@e8c11000 {
|
|
compatible = "arm,cortex-a7-gic";
|
|
reg = <0xe8c11000 0x1000>,
|
|
<0xe8c12000 0x2000>;
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
};
|
|
};
|
|
};
|